V DSS = 55V. R DS(on) = 0.040Ω I D = 28A

Transcription

1 PD- 937C IRLR/U2705 HEXFET Power MOSFET Logic-Leve Gate Drive Utra Low On-Resistance Surface Mount (IRLR2705) Straight Lead (IRLU2705) dvanced Process Technoogy Fast Switching Fuy vaanche Rated G D S V DSS = 55V R DS(on) = 0.040Ω I D = 28 Description Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve the owest possibe on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient device for use in a wide variety of appications. The D-PK is designed for surface mounting using vapor phase, infrared, or wave sodering techniques. The straight ead version (IRFU series) is for through-hoe mounting appications. Power dissipation eves up to.5 watts are possibe in typica surface mount appications. bsoute Maximum Ratings Therma Resistance D-Pak TO-252 I-Pak TO-25 Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 28 I T C = 0 C Continuous Drain Current, V V 20 I DM Pused Drain Current P C = 25 C Power Dissipation 68 W Linear Derating Factor 0.45 W/ C V GS Gate-to-Source Votage ± 6 V E S Singe Puse vaanche Energy mj I R vaanche Current 6 E R Repetitive vaanche Energy 6.8 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) C Parameter Typ. Max. Units R θjc Junction-to-Case 2.2 R θj Case-to-mbient (PCB mount)** 50 C/W R θj Junction-to-mbient ** When mounted on " square PCB (FR-4 or G- Materia ). For recommended footprint and sodering techniques refer to appication note #N //03

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Votage Temp. Coefficient V/ C Reference to 25 C, I D = m V GS = V, I D = 7 R DS(on) Static Drain-to-Source On-Resistance 0.05 W V GS = 5.0V, I D = V GS = 4.0V, I D = 4 V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µ g fs Forward Transconductance S V DS = 25V, I D = 6 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 6V n Gate-to-Source Reverse Leakage -0 V GS = -6V Q g Tota Gate Charge 25 I D = 6 Q gs Gate-to-Source Charge 5.2 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge 4 V GS = 5.0V, See Fig. 6 and 3 t d(on) Turn-On Deay Time 8.9 V DD = 28V t r Rise Time 0 I ns D = 6 t d(off) Turn-Off Deay Time 2 R G = 6.5Ω, V GS = 5.0V t f Fa Time 29 R D =.8Ω, See Fig. L D Interna Drain Inductance 4.5 nh Between ead, 6mm (0.25in.) L S Interna Source Inductance 7.5 G from package and center of die contact C iss Input Capacitance 880 V GS = 0V C oss Output Capacitance 220 pf V DS = 25V C rss Reverse Transfer Capacitance 94 ƒ =.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 28 (Body Diode) showing the G I SM Pused Source Current integra reverse (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 7, V GS = 0V t rr Reverse Recovery Time 76 ns T J = 25 C, I F = 6 Q rr Reverse RecoveryCharge nc di/dt = 0/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L = 6µH R G = 25Ω, I S = 6. (See Figure 2) ƒ I SD 6, di/dt 270/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%. Cacuated continuous current based on maximum aowabe junction temperature; Package imitation current = 20. This is appied for I-PK, L S of D-PK is measured between ead and center of die contact. Uses IRLZ34N data and test conditions. 2

3 I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH 0. T J = 75 C 0. 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J T = 75 C J V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) I D = 27 V GS = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature 3

4 C, Capacitance (pf) V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd C iss C oss = C ds Cgd C oss C rss 0 0 V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) I D = 6 V DS = 44V V DS = 28V FOR TEST CIRCUIT SEE FIGURE Q, Tota Gate Charge (nc) G Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J V GS = 0V V SD, Source-to-Drain Votage (V) I D, Drain Current () 00 OPERTION IN THIS RE LIMITED BY RDS(on) 0 µs 0µs ms T C = 25 C T J = 75 C ms Singe Puse 0 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating rea 4

5 30 LIMITED BY PCKGE V DS R D 25 R G V GS D.U.T. I D, Drain Current () V Puse Width µs Duty Factor 0. % Fig a. Switching Time Test Circuit - V DD 5 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) 0. D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J= P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case 5

6 5V V DS L DRIVER R G D.U.T I S - V DD 20V tp 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS tp E S, Singe Puse vaanche Energy (mj) I D TOP 6.6 BOTTOM 6 V DD = 25V Starting T J, Junction Temperature ( C) Fig 2c. Maximum vaanche Energy Vs. Drain Current I S Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF V Q GS Q GD D.U.T. V - DS V G V GS 3m Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFETS 7

8 Package Outine TO-252 Outine Dimensions are shown in miimeters (inches) 5.46 (.25) 5.2 (.205) 6.73 (.265) 6.35 (.250) (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086).4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) 4.02 (.040).64 (.025) (.245) 5.97 (.235).42 (.4) 9.40 (.370) 6.45 (.245) 5.68 (.224) LED SSIGNMENTS - GTE.52 (.060).5 (.045) 2X.4 (.045) 0.76 (.030) 3X - B (.035) 0.64 (.025) 0.25 (.0) M M B 0.5 (.020) MIN (.023) 0.46 (.08) 2 - DRIN 3 - SOURCE 4 - DRIN 2.28 (.090) 4.57 (.80) NOTES: DIMENSIONING & TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO DIMENSIONS SHOWN RE BEFORE SOLDER DIP, SOLDER DIP MX. 0.6 (.006). Part Marking Information TO-252 (D-PRK) EXMPLE : THIS IS N IRFR20 WITH SSEMBLY LOT CODE 9UP INTERNTIONL RECTIFIER LOGO IRFR 20 FIRST PORTION OF PRT NUMBER 9U P SSEMBLY SECOND PORTION LOT CODE OF PRT NUMBER 8

9 Package Outine TO-25 Outine Dimensions are shown in miimeters (inches) 5.46 (.25) 5.2 (.205).52 (.060).5 (.045) 6.73 (.265) 6.35 (.250) (.245) 5.97 (.235).27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086) 0.58 (.023) 0.46 (.08) 6.45 (.245) 5.68 (.224) LED SSIGNMENTS - GTE 2 - DRIN 3 - SOURCE 4 - DRIN B (.090).9 (.075) 9.65 (.380) 8.89 (.350) NOTES: DIMENSIONING & TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO DIMENSIONS SHOWN RE BEFORE SOLDER DIP, SOLDER DIP MX. 0.6 (.006). 3X.4 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.0) M M B.4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) Part Marking Information TO-25 (I-PRK) EXMPLE : THIS IS N IRFU20 WITH SSEMBLY LOT CODE 9UP INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU 20 9U P FIRST PORTION OF PRT NUMBER SECOND PORTION OF PRT NUMBER 9

10 Tape & Ree Information TO-252 Dimensions are shown in miimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. LL DIMENSIONS RE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EI-48 & EI INCH NOTES :. OUTLINE CONFORMS TO EI mm WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, Te: (3) EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Te: IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 2Z8, Te: (905) IR GERMNY: Saaburgstrasse 57, 6350 Bad Homburg Te: IR ITLY: Via Liguria 49, 07 Borgaro, Torino Te: IR FR EST: K&H Bdg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 7 Te: IR SOUTHEST SI: 35 Outram Road, #-02 Tan Boon Liat Buiding, Singapore 036 Te: Data and specifications subject to change without notice. 4/03

11 Note: For the most current drawings pease refer to the IR website at: