Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Transcription

1 PD 9888 IRL5602S HEXFET Power MOSFET Advanced Process Technoogy Dynamic dv/dt Rating 75 C Operating Temperature PChanne Fast Switching Fuy Avaanche Rated G D S V DSS = 20V R DS(on) = 0.042W I D = 24A Description Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow onresistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The D 2 Pak is a surface mount power package capabe of accommodating die sizes up to HEX4. It provides the highest power capabiity and the owest possibe onresistance in any existing surface mount package. The D 2 Pak is suitabe for high current appications because of its ow interna connection resistance and can dissipate up to 2.0W in a typica surface mount appication. 2 D Pak Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 4.5V 24 I T C = 0 C Continuous Drain Current, V 4.5V 7 A I DM Pused Drain Current 96 P C = 25 C Power Dissipation 75 W Linear Derating Factor 0.5 W/ C V GS GatetoSource Votage ± 8.0 V E AS Singe Puse Avaanche Energy 290 mj I AR Avaanche Current 2 A E AR Repetitive Avaanche Energy 7.5 mj dv/dt Peak Diode Recovery dv/dt ƒ 0.8 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) C Therma Resistance Parameter Typ. Max. Units R qjc JunctiontoCase 2.0 C/W R qja JunctiontoAmbient ( PCB Mounted,steadystate)** //99

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Votage 20 V V GS = 0V, I D = 250µA DV (BR)DSS/DT J Breakdown Votage Temp. Coefficient 0.03 V/ C Reference to 25 C, I D = ma V GS = 4.5V, I D = 2A R DS(on) Static DraintoSource OnResistance W V GS = 2.7V, I D = A V GS = 2.5V, I D = A V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µA g fs Forward Transconductance 2 S V DS = 5V, I D = 2A I DSS DraintoSource Leakage Current 25 V DS = 20V, V GS = 0V µa 250 V DS = 6V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 500 V GS = 8.0V na GatetoSource Reverse Leakage 500 V GS = 8.0V Q g Tota Gate Charge 44 I D = 2A Q gs GatetoSource Charge 8.7 nc V DS = 6V Q gd GatetoDrain ("Mier") Charge 9 V GS = 4.5V, See Fig. 6 and 3 t d(on) TurnOn Deay Time 9.7 V DD = V t r Rise Time 73 I D = 2A ns t d(off) TurnOff Deay Time 53 R G = 6.0W, V GS = 4.5V t f Fa Time 84 R D = 0.8W, See Fig. L S Interna Source Inductance 7.5 nh Between ead, and center of die contact C iss Input Capacitance 460 V GS = 0V C oss Output Capacitance 790 pf V DS = 5V C rss Reverse Transfer Capacitance 370 ƒ =.0MHz, See Fig. 5 SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 24 (Body Diode) showing the A I SM Pused Source Current integra reverse G 96 (Body Diode) pn junction diode. S V SD Diode Forward Votage.4 V T J = 25 C, I S = 2A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 2A Q rr Reverse RecoveryCharge 54 8 nc di/dt = 0A/µs t on Forward TurnOn Time Intrinsic turnon time is negigibe (turnon is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 3.0mH R G = 25W, I AS = 4A. (See Figure 2) ƒ I SD 2A, di/dt 20A/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%. ** When mounted on FR4 board using minimum recommended footprint. For recommended footprint and sodering techniques refer to appication note #AN

3 I D, DraintoSource Current (A) 0 VGS TOP 5V 2V V 7.0V 5.0V 4.5V 2.7V BOTTOM 2.0V 2.0V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, DraintoSource Votage (V) I D, DraintoSource Current (A) 0 VGS TOP 5V 2V V 7.0V 5.0V 4.5V 2.7V BOTTOM 2.0V 2.0V 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, DraintoSource Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, DraintoSource Current (A) 0 T J = 25 C T J = 75 C V DS= 5V 20µs PULSE WIDTH V GS, GatetoSource Votage (V) R DS(on), DraintoSource On Resistance (Normaized) 3.5 I D = 24A V GS = 4.5V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized OnResistance Vs. Temperature 3

4 C, Capacitance (pf) 2800 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED 2400 Crss = Cgd Coss = Cds Cgd 2000 C iss C oss 800 C rss V DS, DraintoSource Votage (V) V GS, GatetoSource Votage (V) I = D 2A V DS =6V V DS =V FOR TEST CIRCUIT SEE FIGURE Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. DraintoSource Votage Fig 6. Typica Gate Charge Vs. GatetoSource Votage I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Votage (V) I I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us ms ms TC = 25 C TJ = 75 C Singe Puse 0 V DS, DraintoSource Votage (V) Fig 7. Typica SourceDrain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 25 V DS R D I D, Drain Current (A) 20 5 R G V GS 4.5V Puse Width µs Duty Factor 0. % D.U.T. V DD T C, Case Temperature ( C) V GS t d(on) t r t d(off) t f % Fig 9. Maximum Drain Current Vs. Case Temperature 90% V DS Therma Response (Z thjc ) 0. D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t Peak T J = P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, JunctiontoCase 5

6 Fig 2a. Uncamped Inductive Test Circuit I AS V DS L R G D.U.T V DD IAS A 20V DRIVER tp 0.0Ω 5V E AS, Singe Puse Avaanche Energy (mj) TOP BOTTOM I D 5.9A A 4A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avaanche Energy Vs. Drain Current tp V (BR)DSS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ 4.5V Q G 2V.2µF.3µF Q GS Q GD D.U.T. V DS V G V GS 3mA Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer V GS R G dv/dt controed by R G I SD controed by Duty Factor "D" D.U.T. Device Under Test V DD * Reverse Poarity of D.U.T for PChanne Driver Gate Drive Period P.W. D = P.W. Period [ V GS =V ] *** D.U.T. I SD Waveform Reverse Recovery Current ReAppied Votage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Rippe 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Leve and 3V Drive Devices Fig 4. For PChanne HEXFETS 7

8 TO263AB Package Detais.40 (.055) MAX..54 (.45).29 (.405) A (.85) 4.20 (.65) B.32 (.052).22 (.048).6 (.400) REF (.255) 6.8 (.243).78 (.070).27 (.050) (.6) 4.73 (.580) 2.79 (.) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.3) 2.32 (.09).40 (.055) 3X.4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) REF (.0) M B A M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. TRR FEED DIRECTION TRL FEED DIRECTION.85 (.073).65 (.065).90 (.429).70 (.42).60 (.063).50 (.059) 4. (.6) 3.90 (.53) 3.50 (.532) 2.80 (.504).60 (.457).40 (.449) 6. (.634) 5.90 (.626).60 (.063).50 (.059).75 (.069).25 (.049) Tape & Ree 5.42 (.609) 5.22 (.60) (.079) (.94) 4 LEAD ASSIGNMENTS GATE 2 DRAIN 3 SOURCE (.045) (.035) (.957) (.94) 4.72 (.36) 4.52 (.78) 8.89 (.350) 3.8 (.50) 2.08 (.082) 2X 7.78 (.700) 2.54 (.0) 2X Part Marking (This is an IRF530S with assemby ot code 9BM ) INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B M A PART NUMBER DATE CODE (YYWW) YY = YEAR WW = WEEK (4.73) MAX (2.362) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (.039) (.96) (.97) MAX. 4 WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, Te: (3) IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Te: IR CANADA: 5 Lincon Court, Brampton, Ontario L6T3Z2, Te: (905) IR GERMANY: Saaburgstrasse 57, 6350 Bad Homburg Te: IR ITALY: Via Liguria 49, 07 Borgaro, Torino Te: IR FAR EAST: K&H Bdg., 2F, 304 NishiIkebukuro 3Chome, ToshimaKu, Tokyo Japan 7 Te: IR SOUTHEAST ASIA: Kim Seng Promenade, Great Word City West Tower, 3, Singapore Te: IR TAIWAN:6 F. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673, Taiwan Te: Data and specifications subject to change without notice. 5/99 8

9 Note: For the most current drawings pease refer to the IR website at: