IRF3808S IRF3808L HEXFET Power MOSFET

Transcription

1 Typical Applications Integrated Starter Alternator 42 Volts Automotive Electrical Systems Benefits Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating G 175 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Description Designed specifically for Automotive applications, this Advanced Planar Stripe HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 175 C junction operating temperature, low RθJC, fast switching speed and improved repetitive avalanche rating. This combination makes the design an extremely efficient and reliable choice for use in higher power Automotive electronic systems and a wide variety of other applications. Absolute Maximum Ratings AUTOMOTIVE MOSFET IRF3808S IRF3808L HEXFET Power MOSFET Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10V 106 I T C = C Continuous Drain Current, V 10V 75 A I DM Pulsed Drain Current 550 P C = 25 C Power Dissipation 200 W Linear Derating Factor 1.3 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 430 mj I AR Avalanche Current 82 A E AR Repetitive Avalanche Energy See Fig.12a, 12b, 15, 16 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.5 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) C D S D 2 Pak IRF3808S PD A V DSS = 75V R DS(on) = 0.007Ω I D = 106A TO-262 IRF3808L Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 C/W R θja Junction-to-Ambient (PCB Mounted, Steady State)** 40 HEXFET(R) is a registered trademark of International Rectifier /08/02

2 IRF3808S/IRF3808L Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 75 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance mω V GS = 10V, I D = 82A V GS(th) Gate Threshold Voltage V V DS = 10V, I D = 250µA g fs Forward Transconductance S V DS = 25V, I D = 82A I DSS Drain-to-Source Leakage Current 20 V µa DS = 75V, V GS = 0V 250 V DS = 60V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 200 V GS = 20V na Gate-to-Source Reverse Leakage -200 V GS = -20V Q g Total Gate Charge I D = 82A Q gs Gate-to-Source Charge nc V DS = 60V Q gd Gate-to-Drain ("Miller") Charge V GS = 10V t d(on) Turn-On Delay Time 16 V DD = 38V t r Rise Time 140 I D = 82A ns t d(off) Turn-Off Delay Time 68 R G = 2.5Ω t f Fall Time 120 V GS = 10V Between lead, D L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 5310 V GS = 0V C oss Output Capacitance 890 pf V DS = 25V C rss Reverse Transfer Capacitance 130 ƒ = 1.0MHz, See Fig. 5 C oss Output Capacitance 6010 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 570 V GS = 0V, V DS = 60V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 1140 V GS = 0V, V DS = 0V to 60V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 106 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 550 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 82A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 82A Q rr Reverse RecoveryCharge nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: C oss eff. is a fixed capacitance that gives the same charging time Repetitive rating; pulse width limited by as C oss while V DS is rising from 0 to 80% V DSS. max. junction temperature. (See fig. 11). Calculated continuous current based on maximum allowable Starting T J = 25 C, L = 0.130mH junction temperature. Package limitation current is 75A. R G = 25Ω, I AS = 82A. (See Figure 12). Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive ƒ I SD 82A, di/dt 310A/µs, V DD V (BR)DSS, avalanche performance. T J 175 C ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). Pulse width 400µs; duty cycle 2%. For recommended footprint and soldering techniques refer to application note #AN

3 I D, Drain-to-Source Current (Α) IRF3808S/IRF3808L I D, Drain-to-Source Current (A) 0 10 TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V I D, Drain-to-Source Current (A) 0 10 TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 137A T J = 175 C T J = 25 C V DS = 15V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) V GS = 10V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance(pF) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRF3808S/IRF3808L 000 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds C rss = C gd C oss = C ds C gd SHORTED I D = 82A V DS = 60V V DS = 37V V DS = 15V 00 0 Ciss Coss V GS, Gate-to-Source Voltage (V) Crss 1 10 V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage T J = 175 C 0 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 25 C µsec 1.00 V GS = 0V V SD, Source-toDrain Voltage (V) 10 1 Tc = 25 C Tj = 175 C Single Pulse 1msec 10msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 IRF3808S/IRF3808L 120 LIMITED BY PACKAGE V DS R D R G V GS D.U.T V DD I D, Drain Current (A) V Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 1 Thermal Response (Z thjc ) 0.1 D = SINGLE PULSE (THERMAL RESPONSE) 2. Peak T J = P DM x Z thjc T C t 1, Rectangular Pulse Duration (sec) Notes: 1. Duty factor D = t 1 / t 2 P DM t 1 t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 V GS(th) Gate threshold Voltage (V) IRF3808S/IRF3808L 15V 800 I D V DS L DRIVER 640 TOP BOTTOM 34A 58A 82A R G 20V tp Fig 12a. Unclamped Inductive Test Circuit tp D.U.T I AS 0.01Ω V (BR)DSS - V DD A E AS, Single Pulse Avalanche Energy (mj) Starting Tj, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy Vs. Drain Current 10 V Q GS Q GD 3.5 V G 3.0 Current Regulator Same Type as D.U.T. Charge Fig 13a. Basic Gate Charge Waveform I D = 250µA 12V.2µF 50KΩ.3µF 1.5 V GS D.U.T. V - DS mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature 6

7 E AR, Avalanche Energy (mj) IRF3808S/IRF3808L 00 Avalanche Current (A) 0 10 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax E E E E E E E-01 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth TOP Single Pulse BOTTOM 10% Duty Cycle I D = 140A Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-5 at 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = T/ Z thjc I av = 2 T/ [1.3 BV Z th ] E AS (AR) = P D (ave) t av Fig 16. Maximum Avalanche Energy Vs. Temperature 7

8 IRF3808S/IRF3808L Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =10V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 17. For N-channel HEXFET power MOSFETs 8

9 IRF3808S/IRF3808L D 2 Pak Package Outline 1.40 (.055) M AX (.415) (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) REF (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) REF (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.) 2X D 2 Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L 9

10 IRF3808S/IRF3808L TO-262 Package Outline TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C 10

11 IRF3808S/IRF3808L D 2 Pak Tape & Reel Information TRR 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.0 73) 1.65 (.0 65) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) M IN. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) M A X. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information.03/

12 Note: For the most current drawings please refer to the IR website at: