SMPS MOSFET. V DSS R DS(on) max I D

Transcription

1 PD A SMPS MOSFET IRFR12N25DPbF IRFU12N25DPbF HEXFET Power MOSFET Applications High frequency DC-DC converters Lead-Free l l V DSS R DS(on) max I D 250V 0.26Ω 14A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN01) Fully Characterized Avalanche Voltage and Current l l l D-Pak IRFR12N25D I-Pak IRFU12N25D Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 14 I T C = 0 C Continuous Drain Current, V V 9.7 A I DM Pulsed Drain Current 56 P C = 25 C Power Dissipation 144 W Linear Derating Factor 0.96 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 9.3 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (1.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.04 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient 1 Notes through are on page /2/04

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 250 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.29 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 0.26 Ω V GS = V, I D = 8.4A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 200V, V GS = 0V 250 V DS = 160V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 V GS = 30V na Gate-to-Source Reverse Leakage -0 V GS = -30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 6.8 S V DS = 25V, I D = 8.4A Q g Total Gate Charge I D = 8.4A Q gs Gate-to-Source Charge nc V DS = 200V Q gd Gate-to-Drain ("Miller") Charge V GS = V, t d(on) Turn-On Delay Time 9.1 V DD = 125V t r Rise Time 25 ns I D = 8.4A t d(off) Turn-Off Delay Time 16 R G = 6.8Ω t f Fall Time 9.2 V GS = V C iss Input Capacitance 8 V GS = 0V C oss Output Capacitance 130 V DS = 25V C rss Reverse Transfer Capacitance 22 pf ƒ = 1.0MHz C oss Output Capacitance 10 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 50 V GS = 0V, V DS = 200V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 130 V GS = 0V, V DS = 0V to 200V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 250 mj I AR Avalanche Current 8.4 A E AR Repetitive Avalanche Energy 14 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 14 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 56 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.5 V T J = 25 C, I S = 8.4A, V GS = 0V t rr Reverse Recovery Time 140 ns T J = 25 C, I F = 8.4A Q rr Reverse RecoveryCharge 7 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFR/U12N25DPbF 0 1 VGS TOP 15V 12V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 0 VGS TOP 15V 12V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V V 1 5.0V µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 14A T J = 175 C T J = 25 C 0. V DS = 15V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance(pF) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRFR/U12N25DPbF 000 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 12 I D = 8.4A V DS V DS V DS = 200V = 125V = 50V 00 0 Ciss Coss V GS, Gate-to-Source Voltage (V) Crss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage T J = 175 C 0 OPERATION IN THIS AREA LIMITED BY R DS (on).00 0µsec 1.00 T J = 25 C V GS = 0V V SD, Source-toDrain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 1msec msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 15 V DS R D 12 R G V GS D.U.T. - V DD I D, Drain Current (A) 9 6 V GS Pulse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit 3 V DS 90% T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc T C t 1, Rectangular Pulse Duration (sec) P DM t 1 t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 15V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM Starting T, Junction Temperature ( J C) I D 3.4A 5.9A 8.4A Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. Q G 50KΩ Q GS Q GD 12V.2µF.3µF D.U.T. V - DS V G V GS 3mA Charge I G I D Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs 7

8 D-Pak (TO-252AA) Package Outline D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH AS SEMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = ASSEMBLY SITE CODE 8

9 I-Pak (TO-251AA) Package Outline I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INT ERNATIONAL RECTIFIER LOGO AS S E MB L Y LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECTIFIER LOGO AS S EMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = ASSEMBLY SITE CODE 9

10 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 7.1mH R G = 25Ω, I AS = 8.4A. ƒ I SD 8.4A, di/dt 150A/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS * When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q1] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.12/04

11 Note: For the most current drawings please refer to the IR website at: