V DSS R DS(on) max I D

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1 PD A IRFR34PbF IRFU34PbF HEXFET Power MOSFET Applications High frequency DC-DC converters Lead-Free l l V DSS R DS(on) max I D V 39mΩ 31A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN1) Fully Characterized Avalanche Voltage and Current l l l D-Pak IRFR34 I-Pak IRFU34 Absolute Maximum Ratings Symbol Parameter Max. Units V DS Drain-Source Voltage V Gate-to-Source Voltage ± 20 I T C = 25 C Continuous Drain V 31 I T C = C Continuous Drain V 22 A I DM Pulsed Drain Current 125 P C = 25 C Maximum Power Dissipation 1 W P A = 25 C Maximum Power Dissipation 3.0 Linear Derating Factor 0.71 mw C dv/dt Peak Diode Recovery dv/dt ƒ 15 V/ns T J Operating Junction and -55 to 175 C T STG Storage Temperature Range Soldering Temperature, for seconds 300 (1.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.4 R θja Junction-to-Ambient (PCB mount)* 40 C/W R θja Junction-to-Ambient 1 Notes through are on page /03/04

2 IRFR/U34PbF T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.11 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance mω = V, I D = 18A (th) Gate Threshold Voltage V V DS =, I D = 250µA 20 V µa DS = V, = 0V I DSS Drain-to-Source Leakage Current 250 V DS = 80V, = 0V, T J = 150 C Gate-to-Source Forward Leakage 200 = 20V I GSS na Gate-to-Source Reverse Leakage -200 = -20V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 33 S V DS = 25V, I D = 18A Q g Total Gate Charge I D = 18A Q gs Gate-to-Source Charge nc V DS = 50V Q gd Gate-to-Drain ("Miller") Charge 11 = V, t d(on) Turn-On Delay Time 12 V DD = 50V t r Rise Time 27 ns I D = 18A t d(off) Turn-Off Delay Time 40 R G = 9.1Ω t f Fall Time 13 = V C iss Input Capacitance 1690 = 0V C oss Output Capacitance 220 V DS = 25V C rss Reverse Transfer Capacitance 26 pf ƒ = 1.0MHz C oss Output Capacitance 1640 = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 130 = 0V, V DS = 80V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 250 = 0V, V DS = 0V to 80V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 140 mj I AR Avalanche Current 18 A Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 31 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 125 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 18A, = 0V t rr Reverse Recovery Time 84 ns T J = 25 C, I F = 18A Q rr Reverse RecoveryCharge 260 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2

3 I D, Drain-to-Source Current (Α) (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFR/U34PbF 0 TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 4.5V 1 20µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 1 20µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 R DS(on), Drain-to-Source On Resistance 3.0 I D = 30A = V T J = 175 C 2.0 T J = 25 C 1.0 V DS = 50V 20µs PULSE WIDTH , Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance (pf) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A), Gate-to-Source Voltage (V) IRFR/U34PbF = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 18A V DS = 80V VDS= 50V VDS= 20V 0 Ciss Coss 12 8 Crss 4 1 V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on).0 T J = 175 C.0 µsec 1.0 T J = 25 C = 0V V SD, Source-toDrain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 1msec msec 1 0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 Thermal Response ( Z thjc ) I D, Drain Current (A) IRFR/U34PbF LIMITED BY PACKAGE R G V DS R D D.U.T. - V DD Pulse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% % t d(on) t r t d(off) t f Fig b. Switching Time Waveforms D = SINGLE PULSE ( THERMAL RESPONSE ) E-006 1E t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 E AS, Single Pulse Avalanche Energy (mj) IRFR/U34PbF V DS L 15V DRIVER I D TOP 7.3A 13A BOTTOM 18A R G 20V tp D.U.T IAS 0.01Ω - V DD A 150 Fig 12a. Unclamped Inductive Test Circuit 50 V (BR)DSS tp Starting T J, Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6

7 IRFR/U34PbF Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs 7

8 IRFR/U34PbF D-Pak (TO-252AA) Package Outline D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S E MB L Y S IT E CODE 8

9 IRFR/U34PbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = ASSEMBLY SITE CODE 9

10 IRFR/U34PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.85mH R G = 25Ω, I AS = 18A. ƒ I SD 18A, di/dt 360A/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. * When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.12/04

11 Note: For the most current drawings please refer to the IR website at:

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