TO-220AB. IRF2807ZPbF. 350 P C = 25 C Maximum Power Dissipation 170 Linear Derating Factor

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1 Features l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free Description This HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. G TO-220AB IRF2807ZPbF IRF2807ZPbF IRF2807ZSPbF IRF2807ZLPbF HEXFET Power MOSFET D S D 2 Pak IRF2807ZSPbF PD A V DSS = 75V R DS(on) = 9.4mΩ I D = 75A TO-262 IRF2807ZLPbF Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 89 A I T C = C Continuous Drain Current, V V (See Fig. 9) 63 I T C = 25 C Continuous Drain Current, V V (Package Limited) 75 I DM Pulsed Drain Current c 350 P C = 25 C Maximum Power Dissipation 70 W Linear Derating Factor. W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy (Thermally Limited) d 60 mj E AS (tested) Single Pulse Avalanche Energy Tested Value i 200 I AR Avalanche Current c See Fig.2a,2b,5,6 A E AR Repetitive Avalanche Energy h mj T J Operating Junction and -55 to 75 C T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 screw Thermal Resistance lbf in (.N m) Parameter Typ. Max. Units R θjc Junction-to-Case 0.90 C/W R θcs Case-to-Sink, Flat, Greased Surface 0.50 R θja Junction-to-Ambient 62 R θja Junction-to-Ambient (PCB Mount, steady state)j 40 HEXFET is a registered trademark of International Rectifier. 07/22/

2 IRF2807Z/S/LPbF T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 75 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient V/ C Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 89 Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance mω V GS = V, I D = 53A f V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA gfs Forward Transconductance 67 S V DS = 25V, I D = 53A I DSS Drain-to-Source Leakage Current 20 µa V DS = 75V, V GS = 0V 250 V DS = 75V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 200 na V GS = 20V Gate-to-Source Reverse Leakage -200 V GS = -20V Q g Total Gate Charge 7 nc I D = 53A Q gs Gate-to-Source Charge 9 29 V DS = 60V Q gd Gate-to-Drain ("Miller") Charge V GS = V f t d(on) Turn-On Delay Time 8 ns V DD = 38V t r Rise Time 79 I D = 53A t d(off) Turn-Off Delay Time 40 R G = 6.2Ω t f Fall Time 45 V GS = V f L D Internal Drain Inductance 4.5 nh Between lead, D 6mm (0.25in.) L S Internal Source Inductance 7.5 from package G and center of die contact S C iss Input Capacitance 3270 pf V GS = 0V C oss Output Capacitance 420 V DS = 25V C rss Reverse Transfer Capacitance 240 ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 590 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 280 V GS = 0V, V DS = 60V, ƒ =.0MHz C oss eff. Effective Output Capacitance 440 V GS = 0V, V DS = 0V to 60V Conditions MOSFET symbol D (Body Diode) A showing the I SM Pulsed Source Current 350 integral reverse G (Body Diode)Ãc p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 53A, V GS = 0V f t rr Reverse Recovery Time ns T J = 25 C, I F = 53A, V DD = 25V Q rr Reverse Recovery Charge nc di/dt = A/µs f t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Limited by T Jmax, starting T J = 25 C, L = 0.2mH, R G = 25Ω, I AS = 53A, V GS =V. Part not recommended for use above this value. ƒ I SD 53A, di/dt 420A/µs, V DD V (BR)DSS, T J 75 C. Pulse width.0ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. This value determined from sample failure population. % tested to this value in production. ˆ This is applied to D 2 Pak, when mounted on " square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN

3 I D, Drain-to-Source Current (Α) G fs, Forward Transconductance (S) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRF2807Z/S/LPbF 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 4.5V 0. 20µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 50 T J = 75 C 25 T J = 25 C 75 T J = 25 C 50 T J = 75 C V DS = 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) I D,Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF2807Z/S/LPbF C iss V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 53A V DS = 60V V DS = 38V V DS = 5V 0 C oss C rss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0 00 T J = 75 C 0 OPERATION IN THIS AREA LIMITED BY R DS (on) µsec T J = 25 C V GS = 0V V SD, Source-to-Drain Voltage (V) 0. Tc = 25 C Tj = 75 C Single Pulse msec msec 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRF2807Z/S/LPbF Limited By Package 2.0 I D = 53A V GS = V T C, Case Temperature ( C) T J, Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Normalized On-Resistance vs. Temperature Thermal Response ( Z thjc ) D = SINGLE PULSE ( THERMAL RESPONSE ) E-006 E t, Rectangular Pulse Duration (sec) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRF2807Z/S/LPbF 5V 300 I D R G V DS 20V V GS tp L D.U.T IAS 0.0Ω DRIVER - V DD A TOP 22A 38A BOTTOM 53A Fig 2a. Unclamped Inductive Test Circuit tp V (BR)DSS Starting T J, Junction Temperature ( C) I AS Fig 2b. Unclamped Inductive Waveforms Fig 2c. Maximum Avalanche Energy vs. Drain Current Q G V Q GS Q GD 5.0 V G Charge Fig 3a. Basic Gate Charge Waveform I D = 250µA Current Regulator Same Type as D.U.T. 50KΩ 2.0 2V.2µF.3µF V GS 3mA D.U.T. V - DS T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 4. Threshold Voltage vs. Temperature Fig 3b. Gate Charge Test Circuit 6

7 E AR, Avalanche Energy (mj) Avalanche Current (A) IRF2807Z/S/LPbF 0 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses 0..0E-08.0E-07.0E-06.0E-05.0E-04.0E-03.0E-02.0E-0 tav (sec) Fig 5. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM % Duty Cycle I D = 53A Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-5 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av Fig 6. Maximum Avalanche Energy vs. Temperature 7

8 IRF2807Z/S/LPbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 7. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Pulse Width µs Duty Factor 0. % Fig 8a. Switching Time Test Circuit V DS 90% % V GS t d(on) t r t d(off) t f Fig 8b. Switching Time Waveforms 8

9 IRF2807Z/S/LPbF TO-220AB Package Outline(Dimensions are shown in millimeters (inches)) TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 789 ASSEMBLED ON WW 9, 2000 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead - Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMB LY LOT CODE PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 9 LINE C TO-220AB package is not recommended for Surface Mount Application. Notes:. For an Automotive Qualified version of this part please seehttp:// 2. For the most current drawing please refer to IR website at 9

10 IRF2807Z/S/LPbF D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE P = DESIGNATES LEAD - FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE Notes:. For an Automotive Qualified version of this part please seehttp:// 2. For the most current drawing please refer to IR website at

11 IRF2807Z/S/LPbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" INTERNAT IONAL RECTIFIER LOGO AS S E MB LY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C OR INTERNAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 997 WEEK 9 A = ASSEMBLY SITE CODE Notes:. For an Automotive Qualified version of this part please seehttp:// 2. For the most current drawing please refer to IR website at

12 IRF2807Z/S/LPbF D 2 Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR.60 (.063).50 (.059) 4. (.6) 3.90 (.53).60 (.063).50 (.059) (.045) (.035) FEED DIRECTION TRL.85 (.073).65 (.065).90 (.429).70 (.42).60 (.457).40 (.449) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) (.957) (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) (.079) (.94) (4.73) MAX (2.362) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (.039) (.96) (.97) MAX. 4 TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 07/20 2

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