SMPS MOSFET. V DSS R DS(on) max I D

Transcription

1 SMPS MOSFET Applications l Switch Mode Power Supply (SMPS) l Motor Drive l Bridge Converters l All Zero Voltage Switching Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Enhanced Body Diode dv/dt Capability PD IRFR3412 IRFU3412 HEXFET Power MOSFET V DSS R DS(on) max I D 0V 0.025Ω 48A D-Pak IRFR3412 I-Pak IRFU3412 Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 48 I T C = 0 C Continuous Drain Current, V V 34 A I DM Pulsed Drain Current 190 P C = 25 C Power Dissipation 140 W Linear Derating Factor 0.95 W/ C V GS Gate-to-Source Voltage ± 20 V dv/dt Peak Diode Recovery dv/dt ƒ 6.4 V/ns T J Operating Junction and -55 to 175 C T STG Storage Temperature Range Soldering Temperature, for second 300(1.6mm from case ) Mounting torqe, 6-32 or M3 screw lbf in (1.1N m) Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 48 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 190 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 29A, V GS = 0V t rr Reverse Recovery Time 68 0 ns T J = 125 C, I F = 29A Q rr Reverse RecoveryCharge nc di/dt = 0A/µs I RRM Reverse RecoveryCurrent A t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 1 1/22/02

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 0 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0. V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance Ω V GS = V, I D = 29A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 1.0 V µa DS = 95V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 V GS = 20V na Gate-to-Source Reverse Leakage -0 V GS = -20V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 25 S V DS = 50V, I D = 29A Q g Total Gate Charge I D = 29A Q gs Gate-to-Source Charge nc V DS = 50V Q gd Gate-to-Drain ("Miller") Charge V GS = V, t d(on) Turn-On Delay Time 19 V DD = 50V t r Rise Time 68 ns I D = 29A t d(off) Turn-Off Delay Time 44 R G = 6.8Ω t f Fall Time 37 V GS = V C iss Input Capacitance 3430 V GS = 0V C oss Output Capacitance 270 V DS = 25V C rss Reverse Transfer Capacitance 150 pf ƒ = 1.0MHz C oss Output Capacitance 40 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 170 V GS = 0V, V DS = 80V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 270 V GS = 0V, V DS = 0V to 80V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 160 mj I AR Avalanche Current 29 A E AR Repetitive Avalanche Energy 14 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.05 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient 1 Notes: Repetitive rating; pulse width limited by max. junction temperature. (See Fig. 11) Starting T J = 25 C, L = 0.38mH, R G = 25Ω, I AS = 29A, (See Figure 12a) ƒ I SD 29A, di/dt 420A/µs, V DD V (BR)DSS, T J 150 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. * When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN

3 I D, Drain-to-Source Current (A) TOP BOTTOM VGS 15V V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 00 0 TOP BOTTOM VGS 15V V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 20µs PULSE WIDTH T J = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 48A 2.5 I D, Drain-to-Source Current (A) 0 1 T = 175 J C T = 25 J C V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRFR/U V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 29A V DS = 80V VDS= 50V VDS= 20V Ciss 8 00 Coss 4 Crss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) 0.0 T J = 175 C 0.0 0µsec 1.0 T J = 25 C V GS = 0V V SD, Source-toDrain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 1msec msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 50 LIMITED BY PACKAGE V DS R D 40 R G V GS D.U.T. - V DD I D, Drain Current (A) V GS Pulse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit V DS 90% T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc T C t 1, Rectangular Pulse Duration (sec) P DM t 1 t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS 20V V GS tp L D.U.T IAS 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp 15V DRIVER - V DD A V (BR)DSS E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 12A 21A 29A Starting T, Junction Temperature ( J C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs 7

8 TO-252AA (D-Pak) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 6.73 (.265) 6.35 (.250) - A (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) (.040) 1.64 (.025) 1.52 (.060) 1.15 (.045) 2X 1.14 (.045) 0.76 (.030) X 6.22 (.245) 5.97 (.235) - B (.035) 0.64 (.025) 0.25 (.0) M A M B.42 (.4) 9.40 (.370) 6.45 (.245) 5.68 (.224) 0.51 (.020) MIN (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 2.28 (.090) 4.57 (.180) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). TO-252AA (D-Pak) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASS EMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN THE ASS EMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A 8

9 TO-251AA (I-Pak) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 1.52 (.060) 1.15 (.045) 6.73 (.265) 6.35 (.250) - A (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN B (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.0) M A M B 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) TO-251AA (I-Pak) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASS EMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE AS SEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A 9

10 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA mm Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.1/02

11 Note: For the most current drawings please refer to the IR website at: