SMPS MOSFET. V DSS R DS(on) max I D

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1 Absolute Maximum Ratings SMPS MOSFET Applications l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l High Frequency Buck Converters for Server Processor Power Synchronous FET l Optimized for Synchronous Buck Converters Including Capacitive Induced Turn-on Immunity Benefits l Ultra-Low Gate Impedance l Very Low RDS(on) at 4.5V V GS l Fully Characterized Avalanche Voltage and Current IRF3709 IRF3709S IRF3709L HEXFET Power MOSFET V DSS R DS(on) max I D 30V 9.0mΩ 90A TO-220AB IRF3709 D 2 Pak IRF3709S PD TO-262 IRF3709L Symbol Parameter Max. Units V DS Drain-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 V I T C = 25 C Continuous Drain Current, V 10V 90 I T C = 100 C Continuous Drain Current, V 10V 57 A I DM Pulsed Drain Current 360 P C = 25 C Maximum Power Dissipationƒ 120 W P A = 25 C Maximum Power Dissipation 3.1 W Linear Derating Factor 0.96 mw/ C T J, T STG Junction and Storage Temperature Range -55 to 150 C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.04 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 R θja Junction-to-Ambient (PCB mount) 40 Notes through are on page /20/01

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 30 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA V GS = 10V, I D = 15A ƒ R DS(on) Static Drain-to-Source On-Resistance mω V GS = 4.5V, I D = 12A ƒ V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA 20 V µa DS = 24V, V GS = 0V I DSS Drain-to-Source Leakage Current 100 V DS = 24V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 200 V GS = 16V na Gate-to-Source Reverse Leakage -200 V GS = -16V T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 53 S V DS = 15V, I D = 30A Q g Total Gate Charge I D = 15A Q gs Gate-to-Source Charge 6.7 nc V DS = 16V Q gd Gate-to-Drain ("Miller") Charge 9.7 V GS = 5.0V ƒ Q oss Output Gate Charge 22 V GS = 0V, V DS = 10V t d(on) Turn-On Delay Time 11 V DD = 15V t r Rise Time 171 I ns D = 30A t d(off) Turn-Off Delay Time 21 R G = 1.8Ω t f Fall Time 9.2 V GS = 4.5V ƒ C iss Input Capacitance 2672 V GS = 0V C oss Output Capacitance 1064 pf V DS = 16V C rss Reverse Transfer Capacitance 109 ƒ = 1.0MHz Avalanche Characteristics Symbol Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 382 mj I AR Avalanche Current 30 A Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 90 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 360 (Body Diode) p-n junction diode. S V T J = 25 C, I S = 30A, V GS = 0V ƒ V SD Diode Forward Voltage 0.82 T J = 125 C, I S = 30A, V GS = 0V ƒ t rr Reverse Recovery Time ns T J = 25 C, I F = 30A, V R =15V Q rr Reverse Recovery Charge nc di/dt = 100A/µs ƒ t rr Reverse Recovery Time ns T J = 125 C, I F = 30A, V R =15V Q rr Reverse Recovery Charge nc di/dt = 100A/µs ƒ 2

3 I D, Drain-to-Source Current (A) VGS TOP 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM2.7V 2.7V I D, Drain-to-Source Current (A) VGS TOP 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM2.7V 2.7V 20µs PULSE WIDTH 1 T J = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 1 T J = 150 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 100 T J = 25 C T J = 150 C V DS= 15V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0 I D = 90A V GS = 10V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance (pf) VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds Crss = Cgd Coss = Cds Cgd C iss C oss SHORTED V GS, Gate-to-Source Voltage (V) I D = 30A V DS= 24V V DS= 15V V DS= 6V C rss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) T J = 150 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) 0 I D, Drain Current (A) 100 OPERATION IN THIS AREA LIMITED BY R DS(on) 10us 100us 1ms 10 10ms TC = 25 C TJ = 150 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 100 LIMITED BY PACKAGE V DS R D 80 R G V GS D.U.T. I D, Drain Current (A) V GS Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit - V DD 20 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thjc ) D = SINGLE PULSE t (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t Peak T J =P DM x Z thjc TC t 1, Rectangular Pulse Duration (sec) PDM t1 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS 20V tp Fig 12a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.01Ω 15V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 13A 19A 30A Starting T, Junction Temperature( J C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs 7

8 TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.1 13) 2.62 (.1 03) (.415) (.405) 3.78 (.149) 3.54 (.139) - A (.1 85) 4.20 (.1 65) - B (.052) 1.22 (.048) (.600) (.584) (.255) 6.10 (.240) (.045) M IN LEAD ASSIGNMENTS 1 - G ATE 2 - D RA IN 3 - S OU R CE 4 - D RA IN (.5 55) (.5 30) 4.06 (.16 0) 3.55 (.14 0) 3X 1.40 (.055) 1.15 (.045) 2.54 (.100) 3X 0.93 (.03 7) 0.69 (.02 7) 0.36 (.0 14) M B A M 3X 2.92 (.115) 2.64 (.104) 0.55 (.022) 0.46 (.018) 2X NOTES: 1 D IME NS IO NING & TO LE RA NC ING PE R A NSI Y14.5M, O U TLINE C O NFO R M S TO JE DEC O UTLIN E TO -220A B. 2 C O N TR O LLING D IM EN SIO N : INC H 4 HE ATSIN K & LE AD M EASU R EM EN TS D O NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE : THIS IS AN IRF1010 W ITH ASSEMBLY LOT C ODE 9B1M INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRF B 1M A PART NUMBER DATE CODE (YYWW) YY = YEAR W W = W EEK 8

9 D 2 Pak Package Outline 1.40 (.055) M AX (.415) (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) REF (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) REF (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.100) 2X D 2 Pak Part Marking Information INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B 1M PART NUMBER DATE CODE (YYW W ) YY = YEAR WW = WEEK A 9

10 TO-262 Package Outline TO-262 Part Marking Information 10

11 D 2 Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) MIN. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MAX. 4 Notes: Repetitive rating; pulse width limited by ƒ Pulse width 400µs; duty cycle 2%. max. junction temperature. This is only applied to TO-220AB package Starting T J = 25 C, L = 0.85mH R G = 25Ω, I AS = 30A. This is applied to D 2 Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information.01/

12 Note: For the most current drawings please refer to the IR website at: