SMPS MOSFET. V DSS R DS(on) max I D

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1 SMPS MOSFET PD A IRFB52N15D IRFS52N15D IRFSL52N15D HEXFET Power MOSFET Applications l High frequency DC-DC converters V DSS R DS(on) max I D 150V 0.032Ω 60A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN1001) Fully Characterized Avalanche Voltage and Current l l l TO-220AB IRFB52N15D D 2 Pak IRFS52N15D TO-262 IRFSL52N15D Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10V 60 I T C = 100 C Continuous Drain Current, V 10V 43 A I DM Pulsed Drain Current 240 P A = 25 C Power Dissipation 3.8 W P C = 25 C Power Dissipation 320 Linear Derating Factor 2.1 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 5.5 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting torqe, 6-32 or M3 screw 10 lbf in (1.1N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.47 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 R θja Junction-to-Ambient 40 Notes through are on page /25/02

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 150 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.16 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance Ω V GS = 10V, I D = 36A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA 25 V µa DS = 150V, V GS = 0V I DSS Drain-to-Source Leakage Current 250 V DS = 120V, V GS = 0V, T J = 150 C Gate-to-Source Forward Leakage 100 V GS = 30V I GSS na Gate-to-Source Reverse Leakage -100 V GS = -30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 19 S V DS = 50V, I D = 36A Q g Total Gate Charge I D = 36A Q gs Gate-to-Source Charge nc V DS = 75V Q gd Gate-to-Drain ("Miller") Charge V GS = 10V, t d(on) Turn-On Delay Time 16 V DD = 75V t r Rise Time 47 ns I D = 36A t d(off) Turn-Off Delay Time 28 R G = 2.5Ω t f Fall Time 25 V GS = 10V C iss Input Capacitance 2770 V GS = 0V C oss Output Capacitance 590 V DS = 25V C rss Reverse Transfer Capacitance 110 pf ƒ = 1.0MHz C oss Output Capacitance 3940 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 260 V GS = 0V, V DS = 120V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 550 V GS = 0V, V DS = 0V to 120V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 470 mj I AR Avalanche Current 36 A E AR Repetitive Avalanche Energy 32 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 60 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 240 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.5 V T J = 25 C, I S = 36A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 36A Q rr Reverse RecoveryCharge nc di/dt = 100A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFB/IRFS/IRFSL52N15D VGS TOP 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V VGS TOP 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V V 1 5.0V µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 60A T J = 175 C T J = 25 C V DS = 15V 300µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) V GS = 10V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance(pF) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRFB/IRFS/IRFSL52N15D V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss 1000 Coss 100 Crss V GS, Gate-to-Source Voltage (V) I D = 36A V DS = 120V V DS = 75V V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175 C µsec T J = 25 C 10 1msec 1.00 V GS = 0V V SD, Source-toDrain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 10msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 70 V DS R D 60 V GS D.U.T. 50 R G - V DD I D, Drain Current (A) Fig 10a. Switching Time Test Circuit V DS 90% 10V Pulse Width 1 µs Duty Factor 0.1 % T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 1 Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) P DM t 1 t 2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc T C t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 15V 900 I D V DS L DRIVER 720 TOP BOTTOM 15A 26A 36A Fig 12a. Unclamped Inductive Test Circuit I AS R G 20V tp tp D.U.T I AS 0.01Ω V (BR)DSS - V DD A E AS, Single Pulse Avalanche Energy (mj) Starting Tj, Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 10 V Q GS Q G Q GD 12V.2µF 50KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs 7

8 TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.1 13) 2.62 (.1 03) (.415) (.405) 3.78 (.149) 3.54 (.139) - A (.18 5) 4.20 (.16 5) - B (.052) 1.22 (.048) (.600) (.584) (.255) 6.10 (.240) (.045) M IN LEAD ASSIGNMENTS 1 - G ATE 2 - D RA IN 3 - S OU RC E 4 - D RA IN (.5 55) (.5 30) 4.06 (.160) 3.55 (.140) 3X 1.40 (.05 5) 1.15 (.04 5) 2.54 (.100) 3X 0.93 (.0 37) 0.69 (.0 27) 0.36 (.014) M B A M 3X 2.92 (.115) 2.64 (.104) 0.55 (.022) 0.46 (.018) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, O UTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 C O N TR O LLIN G D IM E NS ION : INC H 4 H EATS IN K & LEA D M E ASUR E M ENTS D O NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C 8

9 D 2 Pak Package Outline 1.40 (.055) M AX (.415) (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) REF (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) REF (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.100) 2X D 2 Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L 9

10 TO-262 Package Outline TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C 10

11 D 2 Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) MIN. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.72mH R G = 25Ω, I AS = 36A. ƒ I SD 36A, di/dt 400A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 300µs; duty cycle 2%. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE. TO-220 package is not recommended for Surface Mount Application (1.039) (.961) (1.197) MAX. 4 C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. This is only applied to TO-220AB package. This is applied to D 2 Pak, when mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] (IRFB52N15D), & Industrial (IRFS/SL52N15D) market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information.06/

12 Note: For the most current drawings please refer to the IR website at:

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