SMPS MOSFET. V DSS R DS(on) max I D A I DM. 320 P C = 25 C Power Dissipation 260 Linear Derating Factor. V/ns T J

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1 Applications l High frequency DC-DC converters l UPS and Motor Control SMPS MOSFET Benefits l Low Gate-to-Drain Charge to Reduce Switching Losses l Fully Characterized Capacitance Including Effective C OSS to Simplify Design, See App. Note AN) l Fully Characterized Avalanche Voltage and Current l Typical R DSon) = mω D Pak IRF8S PD IRF8S IRF8L HEXFET Power MOSFET V DSS R DSon) max I D V mω 8A TO- IRF8L Absolute Maximum Ratings Parameter Max. Units I T C = C Continuous Drain Current, V V 8i I T C = C Continuous Drain Current, V V A I DM Pulsed Drain Current c 3 P C = C Power Dissipation W Linear Derating Factor.8 W C V GS Gate-to-Source Voltage ± V dvdt Peak Diode Recovery dvdt e Vns T J Operating Junction and - to T STG Storage Temperature Range C Soldering Temperature, for seconds 3.mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case. R θjc Junction-to-Case end of life) g.8 CW R θcs Case-to-Sink, Flat, Greased Surface. R θja Junction-to-Ambient PCB Mount, steady state)j 4 Notes through ˆ are on page

2 IRF8SIRF8L T J = C unless otherwise specified) Parameter Min. Typ. Max. Units V BR)DSS Drain-to-Source Breakdown Voltage V V BR)DSS T J Breakdown Voltage Temp. Coefficient. V C R DSon) Static Drain-to-Source On-Resistance mω V GSth) Gate Threshold Voltage. 4. V I DSS Drain-to-Source Leakage Current µa I GSS Gate-to-Source Forward Leakage na Gate-to-Source Reverse Leakage - T J = C unless otherwise specified) Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 8 V V DS = V, I D = 4A Q g Total Gate Charge 8 I D = 8A Q gs Gate-to-Source Charge nc V DS = 8V Q gd Gate-to-Drain "Miller") Charge V GS = V f t don) Turn-On Delay Time V DD = V t r Rise Time 3 I D = 8A t doff) Turn-Off Delay Time ns R G = 39Ω t f Fall Time V GS = V f C iss Input Capacitance 383 V GS = V C oss Output Capacitance 48 V DS = V C rss Reverse Transfer Capacitance 9 pf ƒ =.MHz C oss Output Capacitance 383 V GS = V, V DS =.V, ƒ =.MHz C oss Output Capacitance 8 V GS = V, V DS = 8V, ƒ =.MHz C oss eff. Effective Output Capacitance 3 V GS = V, V DS = V to 8V e Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energydi 3 mj I AR Avalanche Currentc 4 A E AR Repetitive Avalanche Energy c mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 8 Body Diode) I SM Pulsed Source Current 3 Body Diode)ci V SD Diode Forward Voltage.3 V t rr Reverse Recovery Time 99 ns Q rr Reverse RecoveryCharge 4 nc t on Forward Turn-On Time Intrinsic turn-on time is negligible turn-on is dominated by LSLD) A Conditions V GS = V, I D = µa Reference to C, I D = ma V GS = V, I D = 4A f V DS = V GS, I D = µa V DS = V, V GS = V V DS = V, V GS = V, T J = C V GS = V V GS = -V Conditions MOSFET symbol showing the integral reverse p-n junction diode. T J = C, I S = 8A, V GS = V f T J = C, I F = 8A, V DD = V didt = Aµs f G D S

3 I D, Drain-to-Source Current Α) I D, Drain-to-Source Current A) I D, Drain-to-Source Current A) IRF8SIRF8L VGS TOP V V V.V.V.V 4.V BOTTOM 4.V VGS TOP V V V.V.V.V 4.V BOTTOM 4.V 4.V 4.V. µs PULSE WIDTH Tj = C. V DS, Drain-to-Source Voltage V) Fig. Typical Output Characteristics µs PULSE WIDTH Tj = C. V DS, Drain-to-Source Voltage V) Fig. Typical Output Characteristics 3. I D = 8A T J = C 3. T J = C V DS = V µs PULSE WIDTH V GS, Gate-to-Source Voltage V) R DSon), Drain-to-Source On Resistance Normalized)..... V GS = V T J, Junction Temperature C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current A) C, CapacitancepF) V GS, Gate-to-Source Voltage V) IRF8SIRF8L V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss 8 I D = 8A V DS = 8V V DS = V V DS = V C oss 4 C rss V DS, Drain-to-Source Voltage V) 4 8 Q G Total Gate Charge nc) Fig. Typical Capacitance Vs. Drain-to-Source Voltage Fig. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS on) I SD, Reverse Drain Current A) T J = C T = J C V GS = V V SD,Source-to-Drain Voltage V). Tc = C Tj = C Single Pulse µsec msec msec V DS, Drain-to-Source Voltage V) Fig. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 IRF8SIRF8L 8 LIMITED BY PACKAGE V DS R D V GS D U T R G - V DD I D, Drain Current A) 4 Fig a. Switching Time Test Circuit V DS 9 V Pulse Width µs Duty Factor. T, Case Temperature C C) Fig 9. Maximum Drain Current Vs. Case Temperature V GS t don) t r t doff) t f Fig b. Switching Time Waveforms Thermal Response Z thjc ). D =.... t SINGLE PULSE. Notes. THERMAL RESPONSE). Duty factor D = t t. Peak T J = P DM x Z thjc T C t, Rectangular Pulse Duration sec) P DM t Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 IRF8SIRF8L V I D V DS L DRIVER TOP BOTTOM 8A 3A 4A R G D.U.T I AS - V DD A V tp.ω Fig a. Unclamped Inductive Test Circuit V BR)DSS tp E AS, Single Pulse Avalanche Energy mj) 4 3 Starting Tj, Junction Temperature C) I AS Fig c. Maximum Avalanche Energy Vs. Drain Current Fig b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q GS Q G Q GD V.µF KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit

7 IRF8SIRF8L Peak Diode Recovery dvdt Test Circuit D U T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dvdt controlled by R G Driver same type as D U T I SD controlled by Duty Factor "D" D U T - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current didt D.U.T. V DS Waveform Diode Recovery dvdt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple I SD * V GS = V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs

8 8 3, ),,,,, ),,) *, <, < <., IRF8SIRF8L D Pak Package Outline D Pak Part Marking Information 8

9 IRF8SIRF8L 9 TO- Part Marking Information TO- Package Outline ; 3,,, 3 8., <, <, *,),,, IGBT - GATE - COLLECTOR 3- EMITTER 4- COLLECTOR

10 IRF8SIRF8L D Pak Tape Reel Information TRR..3)..9) 4..) 3.9.3)..3)..9).38.4).34.3) FEED DIRECTION TRL.8.3)..).9.49)..4)..4).4.449)..34).9.)..9)..49).4.9)..) 4.3.9) ) 4..3) 4..8) FEED DIRECTION 3..3).8.4).4.9) ) ) MAX...3) MIN. NOTES. COMFORMS TO EIA-48.. CONTROLLING DIMENSION MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE. Notes Repetitive rating; pulse width limited by max. junction temperature. Starting T J = C, L =.3mH, R G = Ω, I AS = 4A. ƒ I SD 4A, didt Aµs, V DD V BR)DSS, T J C. Pulse width 3µs; duty cycle. Rthjc) end of life) is the maximum measured value after temperature cycles from - to C and is accounted for by the physical wearout of the die attach medium in worse case PCB mounting condition of material soldersubstrate), process and re-flow temperature..4.39) 4.4.9) ) MAX. 4 C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8 V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is A. ˆ When mounted on " square PCB FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS 33 Kansas St., El Segundo, California 94, USA Tel 3) - TAC Fax 3) -93 Visit us at for sales contact information.3

11 Note For the most current drawings please refer to the IR website at httpwww.irf.compackage