V DSS R DS(on) max Qg (typ.) 30V GS = 10V 57nC

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1 PD Applications l Optimized for UPS/Inverter Applications l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l Power Tools HEXFET Power MOSFET V DSS R DS(on) max Qg (typ.) 30V 1.95mΩ@ = V 57nC D Benefits l Very Low R DS(on) at 4.5V l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l Lead-Free S D G TO-220AB G D S Gate Drain Source Absolute Maximum Ratings V DS I T C = 25 C I T C = C I DM P C = 25 C P C = C T J T STG Drain-to-Source Voltage Gate-to-Source Voltage Parameter Continuous Drain V Continuous Drain V Pulsed Drain Current c Maximum Power Dissipation g Maximum Power Dissipation g Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for seconds Mounting torque, 6-32 or M3 screw Max. 30 ± h 190h to (1.6mm from case) lbxin (1.1Nxm) Units V A W W/ C C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case g 0.64 R θcs Case-to-Sink, Flat Greased Surface 0.50 C/W R θja Junction-to-Ambient f 62 Notes through are on page /03/09

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 11 mv/ C R DS(on) Static Drain-to-Source On-Resistance mω = 4.5V, I D = 48A e (th) Gate Threshold Voltage V V DS =, I D = 150µA (th) / T J Gate Threshold Voltage Coefficient -7.8 mv/ C I DSS Drain-to-Source Leakage Current 1.0 µa V DS = 24V, = 0V V DS = 24V, = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage na = 20V Gate-to-Source Reverse Leakage - = -20V gfs Forward Transconductance 140 S V DS = 15V, I D = 48A Q g Total Gate Charge Q gs1 Pre-Vth Gate-to-Source Charge 16 V DS = 15V Q gs2 Post-Vth Gate-to-Source Charge 6.7 nc = 4.5V Q gd Gate-to-Drain Charge 19 I D = 48A Q godr Gate Charge Overdrive 15 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 25.7 Q oss Output Charge 35 nc V DS = 16V, = 0V R G Gate Resistance Ω t d(on) Turn-On Delay Time 36 V DD = 15V, = 4.5Ve t r Rise Time 170 ns I D = 48A t d(off) Turn-Off Delay Time 33 R G = 1.8Ω t f Fall Time 60 See Fig. 14 C iss Input Capacitance 8420 = 0V C oss Output Capacitance 1620 pf V DS = 15V C rss Reverse Transfer Capacitance 650 ƒ = 1.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 520 mj I AR Avalanche Currentc 48 A Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 260h (Body Diode) A I SM Pulsed Source Current 50 (Body Diode)c V SD Diode Forward Voltage 1.0 V t rr Reverse Recovery Time ns Q rr Reverse Recovery Charge nc Conditions = 0V, I D = 250µA Reference to 25 C, I D = 1.0mA = V, I D = 60A e Conditions MOSFET symbol showing the integral reverse p-n junction diode. T J = 25 C, I S = 48A, = 0V e T J = 25 C, I F = 48A, V DD = 15V di/dt = 244A/µs e 2

3 I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 00 0 VGS TOP V 9.0V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 3.0V 0 VGS TOP V 9.0V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 3.0V 3.0V 60µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 3.0V 60µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 120A = V T J = 175 C 1.5 T J = 25 C V DS = 15V 60µs PULSE WIDTH , Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf), Gate-to-Source Voltage (V) = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss I D = 48A V DS = 24V V DS = 15V 8.0 C oss C rss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0 00 T J = 175 C OPERATION IN THIS AREA LIMITED BY R DS (on) 0 µsec T J = 25 C msec 1msec 1 = 0V V SD, Source-to-Drain Voltage (V) 1 Tc = 25 C Tj = 175 C Single Pulse 0 1 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, (th), Drain Current (A) Gate threshold Voltage (V) Limited By Package I D = 150µA I D = 1.0mA I D = 1.0A T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature T J, Temperature ( C ) Fig. Threshold Voltage vs. Temperature 1 D = 0.50 Thermal Response ( Z thjc ) C/W R 1 R 1 R 2 R 2 R 3 R 3 τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i Ri R 4 Ri ( C/W) τi (sec) R SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc E-006 1E t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 τ 4 τ 4 τ C τ

6 R DS(on), Drain-to -Source On Resistance (m Ω) E AS, Single Pulse Avalanche Energy (mj) 12 8 I D = 60A I D TOP 17A 27A BOTTOM 48A T J = 125 C T J = 25 C , Gate -to -Source Voltage (V) Starting T J, Junction Temperature ( C) Fig 12. On-Resistance vs. Gate Voltage Fig 13a. Maximum Avalanche Energy vs. Drain Current 15V tp V (BR)DSS V DS L DRIVER R G 20V tp D.U.T IAS 0.01Ω - V DD A Fig 13b. Unclamped Inductive Test Circuit I AS Fig 13c. Unclamped Inductive Waveforms V DS R D D.U.T. V DS 90% R G - V DD Pulse Width 1 µs Duty Factor 0.1 % % t d(on) t r t d(off) t f Fig 14a. Switching Time Test Circuit Fig 14b. Switching Time Waveforms 6

7 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Current Regulator Same Type as D.U.T. Id Vds 12V.2µF 50KΩ.3µF Vgs D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgodr Qgd Qgs2 Qgs1 Fig 16a. Gate Charge Test Circuit Fig 16b. Gate Charge Waveform 7

8 TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: 8

9 TO-220AB Part Marking Information (;$03/( 7,6,6$1,5) /27&2'( $66(0%/('21::,17($66(0%/</,1(& 1RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$57180%(5 '$7(&2'( <($5 :((. /,1(& Note: For the most current drawing please refer to IR website at: Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.45mH, R G = 25Ω, I AS = 48A. ƒ Pulse width 400µs; duty cycle 2%. When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. R θ is measured at T J approximately 90 C. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 120A. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.07/

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