AUTOMOTIVE MOSFET. 30 Pulsed Drain Current c. I DM P C = 25 C Maximum Power Dissipation 120 Linear Derating Factor

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1 Features l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 175 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax AUTOMOTIVE MOSFET S Description Specifically designed for Automotive applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 175 C junction operating temperature, low RθJC, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.\ The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. Absolute Maximum Ratings Parameter G IRLR2908 IRLU2908 HEXFET Power MOSFET D D-Pak IRLR2908 PD V DSS = 80V R DS(on) = 28mΩ I D = 30A I-Pak IRLU2908 Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 39 A I T C = 0 C Continuous Drain Current, V V (See Fig. 9) 28 I T C = 25 C Continuous Drain Current, V V (Package Limited) 30 Pulsed Drain Current c 150 I DM P C = 25 C Maximum Power Dissipation 120 W Linear Derating Factor 0.77 W/ C V GS Gate-to-Source Voltage ± 16 V E AS Single Pulse Avalanche Energy (Thermally Limited) d 180 mj E AS (tested) Single Pulse Avalanche Energy Tested Value i 250 I AR Avalanche Current c See Fig.12a,12b,15,16 A E AR Repetitive Avalanche Energy h mj dv/dt Peak Diode Recovery dv/dt e 2.3 V/ns T J Operating Junction and -55 to 175 C T STG Storage Temperature Range Soldering Temperature, for seconds Thermal Resistance 300 (1.6mm from case ) Parameter Typ. Max. Units R θjc Junction-to-Case 1.3 C/W R θja Junction-to-Ambient (PCB Mount) j 40 R θja Junction-to-Ambient /13/03

2 IRLR2908/IRLU2908 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 80 V V GS = 0V, I D = 250µA ΒV DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance mω V GS = V, I D = 23A f V GS = 4.5V, I D = 20A f V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA gfs Forward Transconductance 35 S V DS = 25V, I D = 23A I DSS Drain-to-Source Leakage Current 20 µa V DS = 80V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 200 na V GS = 16V Gate-to-Source Reverse Leakage -200 V GS = -16V Q g Total Gate Charge nc I D = 23A Q gs Gate-to-Source Charge V DS = 64V Q gd Gate-to-Drain ("Miller") Charge V GS = 4.5V t d(on) Turn-On Delay Time 12 ns V DD = 40V t r Rise Time 95 I D = 23A t d(off) Turn-Off Delay Time 36 R G = 8.3Ω t f Fall Time 55 V GS = 4.5V f L D Internal Drain Inductance 4.5 nh Between lead, D 6mm (0.25in.) G L S Internal Source Inductance 7.5 from package and center of die contact S C iss Input Capacitance 1890 pf V GS = 0V C oss Output Capacitance 260 V DS = 25V C rss Reverse Transfer Capacitance 35 ƒ = 1.0MHz, See Fig. 5 C oss Output Capacitance 1920 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 170 V GS = 0V, V DS = 64V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 3 V GS = 0V, V DS = 0V to 64V Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 39 Conditions MOSFET symbol D (Body Diode) A showing the I SM Pulsed Source Current 150 integral reverse G (Body Diode)Ãc p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 23A, V GS = 0V f t rr Reverse Recovery Time 75 1 ns T J = 25 C, I F = 23A, V DD = 25V Q rr Reverse Recovery Charge 2 3 nc di/dt = 0A/µs f t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) Notes through ˆ are on page 11 HEXFET is a registered trademark of International Rectifier. 2

3 I D, Drain-to-Source Current (Α) G FS, Forward Transconductance (S) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLR2908/IRLU VGS TOP 15V V 4.5V 4.0V 3.5V 3.0V 2.7V BOTTOM 2.5V 00 0 VGS TOP 15V V 4.5V 4.0V 3.5V 3.0V 2.7V BOTTOM 2.5V 2.5V 2.5V µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics T J = 25 C 0 T J = 175 C T J = 175 C T J = 25 C 20 1 V DS = 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) 0 VDS = V 20µs PULSE WIDTH I D, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRLR2908/IRLU V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 23A V DS = 64V V DS = 40V V DS = 16V C iss C oss C rss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) 0.00 T J = 175 C 0.00 T 1.00 J = 25 C V GS = 0V V SD, Source-to-Drain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 0µsec 1msec msec V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRLR2908/IRLU I D = 38A V GS = 4.5V T C, Case Temperature ( C) T J, Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Normalized On-Resistance vs. Temperature 1 D = 0.50 Thermal Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1E-006 1E t 1, Rectangular Pulse Duration (sec) 1. Duty factor D = t 1 / t 2 P DM t 1 2. Peak T J = P DM x Z thjc T C t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRLR2908/IRLU2908 V DS L 15V DRIVER I D TOP 9.3A 16A BOTTOM 23A R G 20V V GS tp D.U.T IAS 0.01Ω - V DD A 200 Fig 12a. Unclamped Inductive Test Circuit tp V (BR)DSS Starting T J, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy vs. Drain Current V Q GS Q GD 2.5 V G 2.0 Current Regulator Same Type as D.U.T. Charge Fig 13a. Basic Gate Charge Waveform 1.5 I D = 250µA 12V.2µF 50KΩ.3µF 1.0 V GS D.U.T. V - DS mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6

7 E AR, Avalanche Energy (mj) Avalanche Current (A) IRLR2908/IRLU Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses E E E E E E E E-01 tav (sec) Fig 15. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM % Duty Cycle I D = 23A Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-05 at 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc Fig 16. Maximum Avalanche Energy I av = 2DT/ [1.3 BV Z th ] vs. Temperature E AS (AR) = P D (ave) t av 7

8 IRLR2908/IRLU D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Pulse Width 1 µs Duty Factor 0.1 % Fig 18a. Switching Time Test Circuit V DS 90% % V GS t d(on) t r t d(off) t f Fig 18b. Switching Time Waveforms 8

9 IRLR2908/IRLU2908 TO-252AA (D-Pak) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 6.73 (.265) 6.35 (.250) - A (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 1.02 (.040) 1.64 (.025) 1.52 (.060) 1.15 (.045) 2X 1.14 (.045) 0.76 (.030) X 6.22 (.245) 5.97 (.235) - B (.035) 0.64 (.025) 0.25 (.0) M A M B.42 (.4) 9.40 (.370) 6.45 (.245) 5.68 (.224) 0.51 (.020) MIN (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 2.28 (.090) 4.57 (.180) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). TO-252AA (D-Pak) Part Marking Information Notes: This part marking information applies to devices produced before 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P INTERNATIONAL RECTIFIER LOGO IRFU U 1P DATE CODE YEAR = 0 WE EK = 16 AS S E MB L Y LOT CODE Notes: This part marking information applies to devices produced after 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A 9

10 IRLR2908/IRLU2908 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 1.52 (.060) 1.15 (.045) 6.73 (.265) 6.35 (.250) - A (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN - B (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.0) M A M B 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) I-Pak (TO-251AA) Part Marking Information Notes: This part marking information applies to devices produced before 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P INTERNATIONAL RECTIFIER LOGO IRFU U 1P DATE CODE YEAR = 0 WEEK = 16 AS S E MBL Y LOT CODE Notes: This part marking information applies to devices produced after 02/26/2001 EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A

11 IRLR2908/IRLU2908 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by T Jmax, starting T J = 25 C, L = 0.71mH, R G = 25Ω, I AS = 23A, V GS =V. Part not recommended for use above this value. ƒ I SD 23A, di/dt 400A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 1.0ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 0% tested to this value in production. ˆ When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN mm Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q1] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 02/

12 Note: For the most current drawings please refer to the IR website at: