IRFZ48NS IRFZ48NL HEXFET Power MOSFET

Transcription

1 l Advanced Process Technology l Surface Mount (IRFZ48NS) l Low-profile through-hole (IRFZ48NL) l 75 C Operating Temperature l Fast Switching l Fully Avalanche Rated Description Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G IRFZ48NS IRFZ48NL HEXFET Power MOSFET D S PD B V DSS = 55V R DS(on) = 0.04Ω I D = 64A The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRFZ48NL) is available for lowprofile applications. Absolute Maximum Ratings 2 D Pak TO-262 Parameter Max. Units I T C = 25 C Continuous Drain V 64 I T C = 0 C Continuous Drain V 45 A I DM Pulsed Drain Current 2 P A = 25 C Power Dissipation 3.8 W P C = 25 C Power Dissipation 30 W Linear Derating Factor 0.83 W/ C Gate-to-Source Voltage ± 20 V I AR Avalanche Current 32 A E AR Repetitive Avalanche Energy 3 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R qjc Junction-to-Case.5 C/W R qja Junction-to-Ambient ( PCB Mounted,steady-state)** /2/0

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 4 mω = V, I D = 32A (th) Gate Threshold Voltage V V DS =, I D = 250µA g fs Forward Transconductance 24 S V DS = 25V, I D = 32A I DSS Drain-to-Source Leakage Current 25 V µa DS = 55V, = 0V 250 V DS = 44V, = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 = 20V na Gate-to-Source Reverse Leakage -0 = -20V Q g Total Gate Charge 8 I D = 32A Q gs Gate-to-Source Charge 9 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 30 = V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 2 V DD = 28V t r Rise Time 78 I D = 32A ns t d(off) Turn-Off Delay Time 34 R G = 0.85Ω t f Fall Time 50 = V, See Fig. L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 970 = 0V C oss Output Capacitance 470 V DS = 25V C rss Reverse Transfer Capacitance 20 pf ƒ =.0MHz, See Fig. 5 E AS Single Pulse Avalanche Energy mj I AS = 32A, L = 0.37mH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 64 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 2 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 32A, = 0V t rr Reverse Recovery Time 68 0 ns T J = 25 C, I F = 32A Q rr Reverse Recovery Charge nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 0.37mH R G = 25Ω, I AS = 32A. (See Figure 2) ƒ I SD 32A, di/dt 220A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. This is the destructive value not limited to the thermal limit. This is the thermal limited value. ** When mounted on " square PCB ( FR-4 or G- Material ). For recommended soldering techniques refer to application note #AN

3 I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 64A I D, Drain-to-Source Current (A) 0 T J = 25 C T J = 75 C V DS = 25V 20µs PULSE WIDTH , Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current (A) IRFZ48NS/IRFZ48NL C, Capacitance (pf) 3500 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED 3000 Crss = Cgd Coss = Cds Cgd 2500 C 2000 iss C oss 500 C rss 0 0 V DS, Drain-to-Source Voltage (V), Gate-to-Source Voltage (V) I D = 32A V DS = 44V V DS = 27V V DS = V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C = 0 V V SD,Source-to-Drain Voltage (V) 0 0. Tc = 25 C Tj = 75 C Single Pulse 0µsec msec msec 0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Voltage 4

5 I D, Drain Current (A) T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G V DS Pulse Width µs Duty Factor 0. % R D D.U.T. Fig a. Switching Time Test Circuit % t d(on) t r t d(off) t f Fig b. Switching Time Waveforms - V DD Thermal Response (Z thjc ) 0. D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.0Ω 5V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 3A 23A 32A Starting T, Junction Temperature ( J C) I AS Fig 2c. Maximum Avalanche Energy Vs. Drain Current Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ =V] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** = 5.0V for Logic Level and 3V Drive Devices Fig 4. For N-channel HEXFET power MOSFETs 7

8 D 2 Pak Package Outline.40 (.055) M AX..54 (.45).29 (.405) - A (.85) 4.20 (.65) - B -.32 (.052).22 (.048).6 (.400) REF (.255) 6.8 (.243).78 (.070).27 (.050) (.6) 4.73 (.580) 2.79 (.) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.3) 2.32 (.09) 3X.40 (.055).4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) REF (.0) M B A M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.8 (.50) 7.78 (.700) 2.08 (.082) 2X 2.54 (.0) 2X Part Marking Information D 2 Pak INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B M PART NUMBER DATE CODE (YYW W ) YY = YEAR WW = WEEK A 8

9 Package Outline TO-262 Outline Part Marking Information TO

10 Tape & Reel Information D 2 Pak TRR 4. (.6 ) 3.90 (.5 3).60 (.063).50 (.059).60 (.063).50 (.059) (.045) (.035) FEED DIRECTION TRL.85 (.07 3).65 (.06 5).90 (.429).70 (.42).60 (.457).40 (.449) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) (.957) (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) (.079) (.94) (4.73) MAX (2.362) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (.039) (.96) (.97) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.03/0

11 Note: For the most current drawings please refer to the IR website at: