IRF7700GPbF. HEXFET Power MOSFET V DSS R DS(on) max I D

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Alaina Hensley
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1 l Ultra Low On-Resistance l P-Channel MOSFET l Very Small SOIC Package l Low Profile (<.mm) l Available in Tape & Reel l Lead-Free l Halogen-Free Description HEXFET power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the ruggedized device design, that International Rectifier is well known for, provides the designer with an extremely efficient and reliable device for use in battery and load management. The TSSOP-8 package, has 45% less footprint area than the standard SO-8. This makes the TSSOP-8 an ideal device for applications where printed circuit board space is at a premium. The low profile (<.mm) of the TSSOP-8 will allow it to fit easily into extremely thin application environments such as portable electronics and PCMCIA cards. IRF7700GPbF HEXFET Power MOSFET V DSS R DS(on) max I D -20V 0.05@V GS = -4.5V -8.A 0.024@V GS = -2.5V -7.3A PD - 955A TSSOP-8 Absolute Maximum Ratings Parameter Max. Units V DS Drain- Source Voltage -20 V I T A = 25 C Continuous Drain Current, V -4.5V -8. I T A = 70 C Continuous Drain Current, V -4.5V -.8 A I DM Pulsed Drain Current -8 P A = 25 C Power Dissipation.5 P A = 70 C Power Dissipation 0.9 W Linear Derating Factor 0.0 W/ C V GS Gate-to-Source Voltage ± 2 V T J, T STG Junction and Storage Temperature Range -55 to + 50 C Thermal Resistance Parameter Max. Units R θja Maximum Junction-to-Ambientƒ 83 C/W 05/5/09

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage -20 V V GS = 0V, I D = -250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.0 V/ C Reference to 25 C, I D = -ma 0.05 V GS = -4.5V, I D = -8.A R DS(on) Static Drain-to-Source On-Resistance Ω V GS = -2.5V, I D = -7.3A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = -250µA g fs Forward Transconductance -20 S V DS = -V, I D = -8.A I DSS Drain-to-Source Leakage Current -.0 V DS = -V, V GS = 0V µa -25 V DS = -V, V GS = 0V, T J = 70 C I GSS Gate-to-Source Forward Leakage -0 V GS = -2V na Gate-to-Source Reverse Leakage 0 V GS = 2V Q g Total Gate Charge I D = -8.A Q gs Gate-to-Source Charge 5 nc V DS = -V Q gd Gate-to-Drain ("Miller") Charge 9 29 V GS = -5.0V t d(on) Turn-On Delay Time 9 V DD = -V t r Rise Time 40 I D = -.0A ns t d(off) Turn-Off Delay Time 20 R G =.0Ω t f Fall Time 30 V GS = -4.5V C iss Input Capacitance 4300 V GS = 0V C oss Output Capacitance 880 pf V DS = -5V C rss Reverse Transfer Capacitance 580 ƒ = TBDkHz Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol -.5 (Body Diode) showing the A I SM Pulsed Source Current integral reverse G -8 (Body Diode) p-n junction diode. V SD Diode Forward Voltage -.2 V T J = 25 C, I S = -.5A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = -.5A Q rr Reverse RecoveryCharge nc di/dt = 0A/µs D S Notes: Repetitive rating; pulse width limited by max. junction temperature. ƒ When mounted on inch square copper board, t< sec Pulse width 300µs; duty cycle 2%. 2

3 -I D, Drain-to-Source Current (Α) IRF7700GPbF -I D, Drain-to-Source Current (A) 0 VGS TOP -5V -V -4.5V -3.0V -2.7V -2.5V -2.25V BOTTOM -2.0V -2.0V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Voltage (V) -I D, Drain-to-Source Current (A) 0 VGS TOP -5V -V -4.5V -3.0V -2.7V -2.5V -2.25V BOTTOM -2.0V -2.0V 20µs PULSE WIDTH T J = 50 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 T J = 25 C T J = 50 C V DS = -5V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0 I D = -8.A V GS= -4.5V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance (pf) VGS = 0V, f = MHz Ciss = Cgs + Cgd, C ds Crss = Cgd Coss = Cds + Cgd C iss C oss C rss SHORTED -V GS, Gate-to-Source Voltage (V) I D = -8.A V DS =-V 0 0 -V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig. Typical Gate Charge Vs. Gate-to-Source Voltage -I SD, Reverse Drain Current (A) 0 T J = 50 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) -I I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us ms T = 25 C ms C TJ = 50 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 .0 V DS R D -I D, Drain Current (A) T C, Case Temperature ( C) R G V GS V GS Pulse Width µs Duty Factor 0. % D.U.T. V DD Fig a. Switching Time Test Circuit V GS t d(on) t r t d(off) t f % + - Fig 9. Maximum Drain Current Vs. Case Temperature 90% V DS Fig b. Switching Time Waveforms 0 Thermal Response (Z thja ) 0. D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J =P DM x Z thja + TA t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Typical Effective Transient Thermal Impedance, Junction-to-Ambient 5

6 R DS (on), Drain-to-Source On Resistance (Ω) IRF7700GPbF R DS(on), Drain-to -Source On Resistance (Ω) I D = -8.A 0.02 V GS = -2.5V 0.04 V GS = -4.5V V GS, Gate -to -Source Voltage (V) I D, Drain Current (A) Fig. Typical On-Resistance Vs. Gate Voltage Fig 2. Typical On-Resistance Vs. Drain Current Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF Q GS Q GD D.U.T. + V DS - V G V GS -3mA Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 -V GS(th), Variace (V) Power (W) IRF7700GPbF I D = -250µA T J, Temperature ( C) Time (sec) Fig 4. Threshold Voltage Vs. Temperature Fig 5. Typical Power Vs. Time 7

8 TSSOP8 Package Outline Dimensions are shown in milimeters (inches) GGG & % %27+,( < 0 % 2 / 0, 02,0(,2 0,//,0(7(5,&+( 20 0; 0, 20 0; ; ( E F ( ( ( %& %&,(; 05. ( H %& / / ƒ %& ƒ ƒ %& ƒ DDD H % EEE ; FFF GGG H FFF + ;E ;F & EEE & % DDD & 85) / ;/ /(,(7,/(,( 8/,( 27(,0(,2,72/(5&,3(50(<0,0(,25(+2:,,//,0(7(5,&+( &2752//,,0(,2,//,0(7(5 7803/(+,/2&7(+2: 780%72%((7(50,(77803/(+,0(,2(5(0(85(77803/(+,0(,2/,7+(/(/(7+)252/(5,728%757( 287/,(&2)25072-((&287/,(0 Note: For the most current drawing please refer to IR website at 8

9 TSSOP8 Part Marking Information (;03/( 7+,,,5)3%) 35780%(5 7(&2(<:: (0%/<,7(&2( /27&2( 3 /HDG)UHHLQGLFDWRU TSSOP-8 Tape and Reel Information PP PP )((,5(&7,2 27( PP 73( 5((/287/,(&2)25072(, (, Note: For the most current drawing please refer to IR website at Data and specifications subject to change without notice. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.05/

Linear Derating Factor 17 mw/ C V GS Gate-to-Source Voltage ± 12 V T J, T STG Junction and Storage Temperature Range -55 to C

Linear Derating Factor 17 mw/ C V GS Gate-to-Source Voltage ± 12 V T J, T STG Junction and Storage Temperature Range -55 to C l Ultra Low R DS(on) per Footprint Area l Low Thermal Resistance l P-Channel MOSFET l One-third Footprint of SOT-23 l Super Low Profile (