V DSS R DS(on) max I D. 20V GS = 10V 8.9A. 71 P A = 25 C Power Dissipation 2.0 P A = 70 C Power Dissipation Linear Derating Factor

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1 Applications Dual SO-8 MOSFET for POL converters in desktop, servers, graphics cards, game consoles and set-top box PD A IRF895 HEXFET Power MOSFET V DSS R DS(on) max I D 20V 8.3m:@V GS = V 8.9A S 8 D G 2 7 D Benefits l Ultra-Low Gate Impedance l Very Low R DS(on) l Fully Characterized Avalanche Voltage and Current S2 G Top View D2 D2 SO-8 Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 20 V V GS Gate-to-Source Voltage ± 20 I T A = 25 C Continuous Drain Current, V V 8.9 I T A = 70 C Continuous Drain Current, V V 7. A I DM Pulsed Drain Current c 7 P A = 25 C Power Dissipation 2.0 W P A = 70 C Power Dissipation Linear Derating Factor W/ C T J Operating Junction and -55 to 50 C Storage Temperature Range T STG Thermal Resistance Parameter Typ. Max. Units R θjl Junction-to-Drain Lead 42 C/W R θja Junction-to-Ambient f 62.5 Notes through are on page 07/09/08

2 IRF895 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 20 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 0.05 V/ C R DS(on) Static Drain-to-Source On-Resistance mω V GS(th) Gate Threshold Voltage V V GS = 4.5V, I D = 7.A e V DS = V GS, I D = 250µA V GS(th) / T J Gate Threshold Voltage Coefficient -4.8 mv/ C I DSS Drain-to-Source Leakage Current.0 µa V DS = 6V, V GS = 0V 50 V DS = 6V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 0 na V GS = 20V Gate-to-Source Reverse Leakage -0 V GS = -20V gfs Forward Transconductance 2 S V DS = V, I D = 7.A Q g Total Gate Charge Q gs Pre-Vth Gate-to-Source Charge.8 V DS = V Q gs2 Post-Vth Gate-to-Source Charge 0.6 nc V GS = 4.5V Q gd Gate-to-Drain Charge.7 I D = 7.A Q godr Gate Charge Overdrive 0.79 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 2.3 Q oss Output Charge 2.7 nc V DS = V, V GS = 0V t d(on) Turn-On Delay Time 6.0 V DD = 4.5V, V GS = 4.5V t r Rise Time 2 ns I D = 7.A t d(off) Turn-Off Delay Time 7. Clamped Inductive Load t f Fall Time 3.6 C iss Input Capacitance 540 V GS = 0V C oss Output Capacitance 80 pf V DS = V C rss Reverse Transfer Capacitance 9 ƒ =.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy d 5 mj I AR Avalanche Current c 7. A Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 2.5 (Body Diode) A I SM Pulsed Source Current 7 (Body Diode)c V SD Diode Forward Voltage.0 V t rr Reverse Recovery Time 3 9 ns Q rr Reverse Recovery Charge nc Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma V GS = V, I D = 8.9A e Conditions MOSFET symbol D showing the G integral reverse S p-n junction diode. T J = 25 C, I S = 7.A, V GS = 0V e T J = 25 C, I F = 7.A, V DD = V di/dt = 0A/µs e 2

3 I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRF895 0 VGS TOP V 8.0V 5.5V 4.5V 3.5V 3.0V 2.8V BOTTOM 2.5V 0 VGS TOP V 8.0V 5.5V 4.5V 3.5V 3.0V 2.8V BOTTOM 2.5V V 60µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 2.5V 60µs PULSE WIDTH Tj = 50 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0.5 I D = 8.9A V GS = V T J = 50 C.0 T J = 25 C 0. V DS = V 60µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 7.A V DS = 6V V DS = V C iss C oss C rss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on).00 T J = 50 C 0 T J = 25 C.00 V GS = 0V V SD, Source-to-Drain Voltage (V) 0. T A = 25 C Tj = 50 C Single Pulse 0µsec msec msec V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) V GS(th) Gate threshold Voltage (V) IRF I D = 250µA T A, Ambient Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Ambient Temperature Fig. Threshold Voltage vs. Temperature 0 D = 0.50 Thermal Response ( Z thja ) SINGLE PULSE ( THERMAL RESPONSE ) R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri E-006 E t, Rectangular Pulse Duration (sec) R 4 Ri ( C/W) τi (sec) R τ 4 τ 4 τ C τ P DM Notes:. Duty factor D = t / t 2 2. Peak T = P x Z T J DM thja A t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 5

6 R DS(on), Drain-to -Source On Resistance (mω) E AS, Single Pulse Avalanche Energy (mj) IRF I D = 8.9A I D TOP 2.4A 2.9A BOTTOM 7.A 25 T J = 25 C T J = 25 C V GS, Gate -to -Source Voltage (V) Fig 2. On-Resistance vs. Gate Voltage Starting T J, Junction Temperature ( C) Fig 3. Maximum Avalanche Energy vs. Drain Current Current Regulator Same Type as D.U.T. V (BR)DSS 5V tp 50KΩ R G V DS 20V VGS tp L D.U.T I AS 0.0Ω DRIVER - V DD A I AS 2V V GS.2µF 3mA.3µF D.U.T. V - DS Fig 4. Unclamped Inductive Test Circuit and Waveform L D I G I D Current Sampling Resistors Fig 5. Gate Charge Test Circuit V DS V DD - V DS 90% D.U.T % V GS Pulse Width < µs Duty Factor < 0.% V GS t d(on) t r t d(off) t f Fig 6. Switching Time Test Circuit Fig 7. Switching Time Waveforms 6

7 IRF895 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 6. Gate Charge Waveform 7

8 IRF895 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f I Q gs 2 V in f i g ( ) Q g V g f Q oss 2 V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8

9 IRF895 SO-8 Package Outline(Mosfet & Fetky) Dimensions are shown in milimeters (inches) ' % ',0,&(6 0, 0$; 0,//,0(7(56 0, 0$; $ $ $ ( >@ $ E F ' ( H %$6,& %$6,& H %$6,& %$6,& ; H. / \ ƒ ƒ ƒ ƒ H $.[ƒ & \ ;E $ >@ ;/ ;F >@ & $ % 27(6 ',0(6,2,* 72/(5$&,*3(5$60(<0 &2752//,*',0(6,2,//,0(7(5 ',0(6,26$5(62:,,//,0(7(56>,&(6@ 287/,(&2) ('(&287/,(06$$ ',0(6,2'2(627,&/8'(02/' ,26 02/' ,262772(;&(('>@ ',0(6,2'2(627,&/8'(02/' ,26 02/' ,262772(;&(('>@ ',0(6,2,67(/(*72)/($')2562/'(5,*72 $68%675$7( >@ )22735,7 ;>@ ;>@ ;>@ SO-8 Part Marking Information (;$03/(7,6,6$,5)026)(7,7(5$7,2$/ 5(&7,),(5 /2*2 ) ;;;; '$7(&2'(<:: 3 ',6*$7(6/($')5(( 352'8&7237,2$/ < /$67',*,72)7(<($5 :: :((. $ $66(0%/<6,7(&2'( /27&2'( 3$5780%(5 Note: For the most current drawing please refer to IR website at: 9

10 IRF895 SO-8 Tape and Reel Dimensions are shown in millimeters (inches) TERMINAL NUMBER 2.3 (.484 ).7 (.46 ) 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES:. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-48 & EIA (2.992) MAX. NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-48 & EIA (.566 ) 2.40 (.488 ) Note: For the most current drawing please refer to IR website at: Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.59mH, R G = 25Ω, I AS = 7.A. ƒ Pulse width 400µs; duty cycle 2%. When mounted on inch square copper board. R θ is measured at T J of approximately 90 C. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 07/2008