IRF6602/IRF6602TR1 HEXFET Power MOSFET

Transcription

1 l Application Specific MOSFETs l Ideal for CPU Core DC-DC Converters l Low Conduction Losses l Low Switching Losses l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible l Compatible with existing Surface Mount Techniques PD C IRF6602/IRF6602TR1 HEXFET Power MOSFET V DSS R DS(on) max Qg 20V 13mΩ@V GS = 10V 12nC 19mΩ@V GS = 4.5V MQ DirectFET ISOMETRIC Applicable DirectFET Package/Layout Pad (see p.9, 10 for details) SQ SX ST MQ MX MT Description The IRF6602 combines the latest HEXFET Power MOSFET Silicon technology with the advanced DirectFET TM packaging to achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%. The IRF6602 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors operating at higher frequencies. The IRF6602 has been optimized for parameters that are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket. Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 20 V V GS Gate-to-Source Voltage ±20 I T C = 25 C Continuous Drain Current, V 10V 48 I T A = 25 C Continuous Drain Current, V 10V 11 I T A = 70 C Continuous Drain Current, V 10V 8.9 A I DM Pulsed Drain Current c 89 P A = 25 C Power Dissipation g 2.3 W P A = 70 C Power Dissipation g 1.5 P C = 25 C Power Dissipation 42 Linear Derating Factor W/ C T J Operating Junction and -40 to 150 C Storage Temperature Range T STG Thermal Resistance Parameter Typ. Max. Units R θja Junction-to-Ambient f 55 R θja Junction-to-Ambient g 12.5 R θja Junction-to-Ambient h 20 C/W R θjc Junction-to-Case i 3.0 R θj-pcb Junction-to-PCB Mounted 1.0 Notes through are on page /29/05

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 20 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 22 mv/ C R DS(on) Static Drain-to-Source On-Resistance mω V GS = 4.5V, I D = 8.8A e V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA V GS(th) Gate Threshold Voltage Coefficient -4.4 mv/ C V DS = 20V, V GS = 0V I DSS Drain-to-Source Leakage Current 20 µa V DS = 16V, V GS = 0V 125 V DS = 16V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 200 na V GS = 20V Gate-to-Source Reverse Leakage -200 V GS = -20V gfs Forward Transconductance 20 S V DS = 10V, I D = 8.8A Q g Total Gate Charge Q gs1 Pre-Vth Gate-to-Source Charge 3.5 V DS = 10V Q gs2 Post-Vth Gate-to-Source Charge 1.3 nc V GS = 4.5V Q gd Gate-to-Drain Charge 4.2 I D = 8.8A Q godr Gate Charge Overdrive 3.0 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 5.5 Q oss Output Charge 19 nc V DS = 16V, V GS = 0V R G Gate Resistance Ω t d(on) Turn-On Delay Time 33 V DD = 15V, V GS = 4.5Ve t r Rise Time 6.0 I D = 8.8A t d(off) Turn-Off Delay Time 14 ns Clamped Inductive Load t f Fall Time 12 C iss Input Capacitance 1420 V GS = 0V C oss Output Capacitance 960 pf V DS = 10V C rss Reverse Transfer Capacitance ƒ = 1.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 97 mj I AR Avalanche Currentc 8.8 A E AR Repetitive Avalanche Energy c 4.2 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 48 (Body Diode) A I SM Pulsed Source Current 380 (Body Diode)c V SD Diode Forward Voltage V t rr Reverse Recovery Time ns Q rr Reverse Recovery Charge nc Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = 1mA V GS = 10V, I D = 11A e Conditions MOSFET symbol showing the integral reverse G p-n junction diode. S T J = 25 C, I S = 8.8A, V GS = 0V e T J = 25 C, I F = 8.8A di/dt = A/µs e D 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRF6602/IRF6602TR1 0 VGS TOP 10V 5.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V 0 VGS TOP 10V 5.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V V V 20µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 1 20µs PULSE WIDTH Tj = 150 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics.00 T J = 150 C 2.0 I D = 11A T J = 25 C V DS = 15V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) V GS = 10V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF6602/IRF6602TR V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 8.8A V DS = 16V V DS = 10V Ciss Coss 3.0 Crss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) T = 150 J C 10 T = 25 J C 1 V GS = 0 V V SD,Source-to-Drain Voltage (V) Tc = 25 C Tj = 150 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) µsec 1msec 10msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 V GS(th) Gate threshold Voltage (V) IRF6602/IRF6602TR I D, Drain Current (A) I D = 250µA T A, Ambient Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current Vs. Ambient Temperature Fig 10. Threshold Voltage Vs. Temperature Thermal Response (Z thja ) 10 1 D = P DM t 1 t 2 SINGLE PULSE (THERMAL RESPONSE) 2. Peak T J = P DM x Z thja T A t 1, Rectangular Pulse Duration (sec) Notes: 1. Duty factor D = t 1 / t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 15V 250 I D V DS L DRIVER 200 TOP BOTTOM 3.9A 7.0A 8.8A R G 20V V GS tp D.U.T IAS 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp - V DD A V (BR)DSS E AS, Single Pulse Avalanche Energy (mj) Starting Tj, Junction Temperature ( C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms V DS L D V DD - Current Regulator Same Type as D.U.T. 50KΩ V GS Pulse Width < 1µs Duty Factor < 0.1% D.U.T 12V.2µF.3µF Fig 14a. Switching Time Test Circuit D.U.T. V - DS V DS 90% V GS 3mA I G I D Current Sampling Resistors 10% V GS t d(on) t r t d(off) t f Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6

7 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =10V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform 7

8 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f i g ( ) Q g V g f Q oss 2 V in f I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q1. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q1 turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8

9 DirectFET Outline Dimension, MQ Outline (Medium Size Can, Q-Designation) Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. NOTE: CONTROLLING DIMENSIONS ARE IN MM CODE A B C D E F G H J K L M N P DIMENSIONS METRIC IMPERIAL MIN MAX ÃMIN ÃMAX

10 DirectFET Board Footprint, MQ Outline (Medium Size Can, Q-Designation) Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. 10

11 DirectFET Tape and Reel Dimension (Showing Component Orientation) IRF6602/IRF6602TR1 NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6602). For 0 parts on 7" reel, order IRF6602TR1 REEL DIMENSIONS STANDARD OPTION (QTY 4800) TR1 OPTION (QTY 0) METRIC IMPERIAL METRIC IMPERIAL CODE A B C D E F G H MIN MAX MIN MAX MIN MAX MIN MAX

12 DirectFET Part Marking Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 2.5mH R G = 25Ω, I AS = 8.8A. (See Figure 14). ƒ Pulse width 400µs; duty cycle 2%. Surface mounted on 1 in. square Cu board. Used double sided cooling, mounting pad. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. T C measured with thermal couple mounted to top (Drain) of part. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information. 03/

13 Note: For the most current drawings please refer to the IR website at: