IRF6608. Absolute Maximum Ratings Max. Thermal Resistance. HEXFET Power MOSFET V DSS R DS(on) max Qg. 30V GS = 10V 16nC GS = 4.

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1 PD 94727B l pplication Specific MOSFETs l Ideal for CPU Core DCDC Converters l Low Conduction Losses l Low Switching Losses l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible l Compatible with existing Surface Mount Techniques HEXFET Power MOSFET V DSS R DS(on) max Qg 30V 9.0mΩ@V GS = V 6nC mω@v GS = 4.5V ST DirectFET ISOMETRIC pplicable DirectFET Outline and Substrate Outline (see p.7, 8 for details) SQ SX ST MQ MX MT Description The combines the latest HEXFET Power MOSFET Silicon technology with the advanced DirectFET TM packaging to achieve the lowest onstate resistance in a package that has the footprint of a MICRO8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infrared or convection soldering techniques, when application note N35 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%. The balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DCDC converters that power the latest generation of processors operating at higher frequencies. The has been optimized for parameters that are critical in synchronous buck converters including Rds(on), gate charge and Cdv/dtinduced turn on immunity. The has been optimized for parameters that are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket. bsolute Maximum Ratings Parameter Max. Units V DS DraintoSource Voltage 30 V V GS GatetoSource Voltage ±2 I T C = 25 C Continuous Drain Current, V V 55 I T = 25 C Continuous Drain Current, V V 3 I T = 70 C Continuous Drain Current, V V I DM Pulsed Drain Current c 0 P = 25 C Power Dissipation g 2. P = 70 C Power Dissipation g.4 W P C = 25 C Power Dissipation Linear Derating Factor W/ C T J Operating Junction and 40 to 50 C Storage Temperature Range T STG Thermal Resistance Parameter Typ. Max. Units R θj Junctiontombient fj 58 R θj Junctiontombient gj 2.5 R θj Junctiontombient hj 20 C/W R θjc JunctiontoCase ij 3.0 R θjpcb JunctiontoPCB Mounted.0 Notes through ˆ are on page 2 3/3/04

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS DraintoSource Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 29 mv/ C Reference to 25 C, I D = m R DS(on) Static DraintoSource OnResistance mω V GS = V, I D = 3 e 8.0 V GS = 4.5V, I D = e V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ V GS(th) / T J Gate Threshold Voltage Coefficient 5.4 mv/ C I DSS DraintoSource Leakage Current 30 µ V DS = 24V, V GS = 0V 0 V DS = 24V, V GS = 0V, T J = 25 C I GSS GatetoSource Forward Leakage 0 n V GS = 2V GatetoSource Reverse Leakage 0 V GS = 2V gfs Forward Transconductance 28 S V DS = 5V, I D = 8.8 Q g Total Gate Charge 6 24 Q gs PreVth GatetoSource Charge 4.6 V DS = 5V Q gs2 PostVth GatetoSource Charge.4 nc V GS = 4.5V Q gd GatetoDrain Charge 5.3 I D = 8.8 Q godr Gate Charge Overdrive 4.7 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 6.7 Q oss Output Charge nc V DS = 5V, V GS = 0V t d(on) TurnOn Delay Time 3 V DD = 5V, V GS = 4.5Ve t r Rise Time 2 I D = 8.8 t d(off) TurnOff Delay Time 6 ns Clamped Inductive Load t f Fall Time 3.4 C iss Input Capacitance 220 V GS = 0V C oss Output Capacitance 440 pf V DS = 5V C rss Reverse Transfer Capacitance 260 ƒ =.0MHz valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energyd 54 mj I R valanche Currentc 8.8 E R Repetitive valanche Energy c 0.2 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 3 (Body Diode) I SM Pulsed Source Current 0 (Body Diode)c V SD Diode Forward Voltage V t rr Reverse Recovery Time 3 47 ns Q rr Reverse Recovery Charge nc Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L =.38mH R G = 25Ω, I S = 8.8. ƒ Pulse width 400µs; duty cycle 2%. Surface mounted on in. square Cu board. Conditions V GS = 0V, I D = 250µ Conditions MOSFET symbol showing the integral reverse pn junction diode. T J = 25 C, I S = 8.8, V GS = 0V e T J = 25 C, I F = 8.8 di/dt = 0/µs e Used double sided cooling, mounting pad. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. T C measured with thermal couple mounted to top (Drain) of part. ˆ R θ is measured at T J of approximately 90 C. 2 G D S

3 C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (Α) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current () I D, DraintoSource Current () 0 VGS TOP V 7.0V 4.5V 3.8V 3.5V 3.2V 2.9V BOTTOM 2.7V 0 2.7V 2.7V 30µs PULSE WIDTH Tj = 25 C VGS TOP V 7.0V 4.5V 3.8V 3.5V 3.2V 2.9V BOTTOM 2.7V 30µs PULSE WIDTH Tj = 50 C Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0.0 T J = 50 C 2.0 I D = 2 V GS = V.5.0 T J = 25 C.0 V DS = 20V 30µs PULSE WIDTH V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 2 I D = 8.8 V DS = 24V VDS= 5V Ciss Coss Crss Q V DS, DraintoSource Voltage (V) G Total Gate Charge (nc) Fig 5. Typical Capacitance vs.draintosource Voltage Fig 6. Typical Gate Charge vs.gatetosource Voltage 3

4 I D, Drain Current () V GS(th) Gate threshold Voltage (V) I D, DraintoSource Current () OPERTION IN THIS RE LIMITED BY R DS (on) I SD, Reverse Drain Current () T J = 50 C.0 T J = 25 C.0 V GS = 0V V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Tc = 25 C Tj = 50 C Single Pulse 0µsec msec msec V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating rea I D = 250µ T J, Junction Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature Thermal Response ( Z thj ) D = SINGLE PULSE ( THERML RESPONSE ) R R 2 R 3 R R 2 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri E006 E t, Rectangular Pulse Duration (sec) R 4 Ri ( C/W) τi (sec) R Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthja Tc Fig. Maximum Effective Transient Thermal Impedance, Junctiontombient 4 τ 4 τ 4 τ C τ

5 R DS(on), Drainto Source On Resistance ( Ω) E S, Single Pulse valanche Energy (mj) I D TOP BOTTOM I D = V GS, Gate to Source Voltage (V) Starting T J, Junction Temperature ( C) Fig 2. OnResistance Vs. Gate Voltage Fig 3c. Maximum valanche Energy Vs. Drain Current 5V L D V DS R G V DS 20V V GS tp L D.U.T I S 0.0Ω DRIVER V DD Fig 3a. Unclamped Inductive Test Circuit V GS Pulse Width < µs Duty Factor < 0.% D.U.T V DD tp V (BR)DSS Fig 4a. Switching Time Test Circuit V DS 90% % V GS I S t d(on) t r t d(off) t f Fig 3b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. Fig 4b. Switching Time Waveforms Vds Id 2V.2µF 50KΩ.3µF Vgs D.U.T. V DS V GS Vgs(th) 3m I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 5. Gate Charge Test Circuit Fig 6. Gate Charge Waveform 5

6 D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G di/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Repplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 7. Diode Reverse Recovery Test Circuit for NChannel HEXFET Power MOSFETs DirectFET Substrate and PCB Layout, ST Outline (Small Size Can, TDesignation). Please see DirectFET application note N35 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. Drain 2 Drain 3 Source 4 Source 5 Gate 6 Drain 7 Drain

7 DirectFET Outline Dimension, ST Outline (Small Size Can, TDesignation). Please see DirectFET application note N35 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. Note: Controlling dimensions are in mm CODE B C D E F G H J K L M N P DIMENSIONS METRIC IMPERIL O DirectFET Part Marking 7

8 DirectFET Tape & Reel Dimension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF668). For 00 parts on 7" reel, order IRF668TR CODE B C D E F G H REEL DIMENSIONS STNDRD OPTION (QTY 4800) TR OPTION (QTY 00) METRIC IMPERIL METRIC IMPERIL Loaded Tape Feed Direction NOTE: CONTROLLING DIMENSIONS IN MM CODE B C D E F G H DIMENSIONS METRIC IMPERIL Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) TC Fax: (3) Visit us at for sales contact information.3/04 8

9 Note: For the most current drawings please refer to the IR website at: