Description Absolute Maximum Ratings Parameter Max. Units Thermal Resistance Parameter Typ. Max. Units

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1 l dvanced Process Technology l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l PChannel l Fully valanche Rated l LeadFree Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications G PD IRF9Z34NPbF HEXFET Power MOSFET D S V DSS = 55V R DS(on) = 0 Ω I D = 9 The TO220 package is universally preferred for all commercialindustrial applications at power dissipation levels to approximately 50 watts The low thermal resistance and low package cost of the TO220 TO220B contribute to its wide acceptance throughout the industry bsolute Maximum Ratings Parameter Max Units I T C = 25 C Continuous Drain Current, V V 9 I T C = 0 C Continuous Drain Current, V V 4 I DM Pulsed Drain Current 68 P C = 25 C Power Dissipation 68W Linear Derating Factor 0 45 W/ C V GS GatetoSource Voltage ± 20 V E S Single Pulse valanche Energy 80 mj I R valanche Current E R Repetitive valanche Energy 6 8mJ dv/dt Peak Diode Recovery dv/dt ƒ 5 0 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 ( 6mm from case ) Mounting torque, 632 or M3 screw lbf in ( N m) Thermal Resistance Parameter Typ Max Units R θjc JunctiontoCase 2 2 R θcs CasetoSink, Flat, Greased Surface 0 50 C/W R θj Junctiontombient 62 02/05/04

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min Typ Max Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp Coefficient 0 05 V/ C Reference to 25 C, I D = m R DS(on) Static DraintoSource OnResistance 0 Ω V GS = V, I D = V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance 4 2 S V DS = 25V, I D = I DSS DraintoSource Leakage Current 25 V µ DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 0 V GS = 20V n GatetoSource Reverse Leakage 0 V GS = 20V Q g Total Gate Charge 35 I D = Q gs GatetoSource Charge 7 9 nc V DS = 44V Q gd GatetoDrain ("Miller") Charge 6 V GS = V, See Fig 6 and 3 t d(on) TurnOn Delay Time 3 V DD = 28V t r Rise Time 55 I D = ns t d(off) TurnOff Delay Time 30 R G = 3Ω t f Fall Time 4 R D = 2 6Ω, See Fig Between lead, L D Internal Drain Inductance 4 5 6mm (0 25in ) nh G from package L S Internal Source Inductance 7 5 and center of die contact C iss Input Capacitance 620 V GS = 0V C oss Output Capacitance 280 pf V DS = 25V C rss Reverse Transfer Capacitance 40 ƒ = 0MHz, See Fig 5 D S SourceDrain Ratings and Characteristics Parameter Min Typ Max Units Conditions D I S Continuous Source Current MOSFET symbol 9 (Body Diode) showing the I SM Pulsed Source Current integral reverse G 68 (Body Diode) pn junction diode S V SD Diode Forward Voltage 6 V T J = 25 C, I S =, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = Q rr Reverse RecoveryCharge 60 nc di/dt = 0/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max junction temperature ( See fig ) Starting T J = 25 C, L = 3 6mH R G = 25Ω, I S = (See Figure 2) ƒ I SD, di/dt 290/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%

3 I D, DraintoSource Current () 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T c = 25 C 0. 0 V DS, DraintoSource Voltage (V) I D, DraintoSource Current () 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T C = 75 C 0. 0 V DS, DraintoSource Voltage (V) Fig Typical Output Characteristics Fig 2 Typical Output Characteristics I D, DraintoSource Current () 0 T = 25 C J V DS = 25V 20µs PULSE WIDTH V, GatetoSource Voltage (V) GS T = 75 C J R DS(on), DraintoSource On Resistance (Normalized) I = 7 D V GS = V T J, Junction Temperature ( C) Fig 3 Typical Transfer Characteristics Fig 4 Normalized OnResistance Vs Temperature

4 C, Capacitance (pf) 200 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 00 C oss = C ds Cgd 800 C iss 600 Coss 400 C rss V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I D = V DS = 44V V DS = 28V FOR TEST CIRCUIT 0 SEE FIGURE Q G, Total Gate Charge (nc) Fig 5 Typical Capacitance Vs DraintoSource Voltage Fig 6 Typical Gate Charge Vs GatetoSource Voltage I SD, Reverse Drain Current () 0 T = 75 C J T = 25 C J V GS = 0V V SD, SourcetoDrain Voltage (V) I D, Drain Current () 00 0 OPERTION IN THIS RE LIMITED BY RDS(on) T C = 25 C T J = 75 C ms Single Pulse 0 V, DraintoSource Voltage (V) DS µs 0µs ms Fig 7 Typical SourceDrain Diode Forward Voltage Fig 8 Maximum Safe Operating rea

5 20 V DS R D I D, Drain Current () T C, Case Temperature ( C) R G V GS V Pulse Width µs Duty Factor 0. % D U T Fig a Switching Time Test Circuit V GS t d(on) t r t d(off) t f % V DD 90% Fig 9 Maximum Drain Current Vs Case Temperature V DS Fig b Switching Time Waveforms Thermal Response (Z thjc ) 0. D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t Peak T J= P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig Maximum Effective Transient Thermal Impedance, JunctiontoCase

6 Fig 2a Unclamped Inductive Test Circuit I S V DS L R G D.U.T V DD IS 20V DRIVER tp 0.0Ω 5V E S, Single Pulse valanche Energy (mj) ID TOP BOTTOM Starting T J, Junction Temperature ( C) Fig 2c Maximum valanche Energy Vs Drain Current tp V (BR)DSS Fig 2b Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q G 2V.2µF 50KΩ.3µF Q GS Q GD D.U.T. V DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 3a Basic Gate Charge Waveform Fig 3b Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D U T* ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D U T Device Under Test V DD * Reverse Polarity of D U T for PChannel Driver Gate Drive Period P.W. D = P.W. Period [ ] *** V GS =V D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt [ ] V DD Repplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% [ ] I SD *** V GS = 5 0V for Logic Level and 3V Drive Devices Fig 4 For PChannel HEXFETS

8 TO220B Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) (.255) 6. (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LED SSIGNMENTS LED SSIGNMENTS HEXFET IGBTs, CoPCK GTE GTE 2 DRIN GTE 2 DRIN 3 SOURCE 2 COLLECTOR 3 SOURCE 4 DRIN 3 EMITTER 4 DRIN 4 COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.0) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) DIMENSIONING & TOLERNCING PER NSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO220B. 2 CONTROLLING DIMENSION : INCH 4 HETSINK & LED MESUREMENTS DO NOT INCLUDE BURRS. TO220B Part Marking Information EXMPLE: T HIS IS N IRF LOT CODE 789 S S EMBLED ON WW 9, 997 IN THE SSEMBLY LINE "C" Note: "P" in assembly line position indicates "LeadFree" INT ERNT IONL RE CT IFIER LOGO S S E MB L Y LOT CODE PRT NUMBER DTE CODE YER 7 = 997 WEEK 9 LINE C Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) TC Fax: (3) Visit us at for sales contact information.02/04

9 Note: For the most current drawings please refer to the IR website at: