30V GS = 10V 48nC GS = 4.5V

Transcription

1 l Application Specific MOSFETs l Ideal for CPU Core C-C Converters l Low Conduction Losses l High Cdv/dt Immunity l Low Profile (<0.7 mm) l ual Sided Cooling Compatible l Compatible with existing Surface Mount Techniques MT Applicable irectfet Outline and Substrate Outline (see p.9,10 for details) P F IRF6603 HEXFET Power MOSFET V SS R S(on) max Qg(typ.) 30V 3.4mΩ@V GS = 10V 48nC 5.5mΩ@V GS = 4.5V irectfet ISOMETRIC SQ SX ST MQ MX MT escription The IRF6603 combines the latest HEXFET Power MOSFET Silicon technology with the advanced irectfet TM packaging to achieve the lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The irectfet package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and process. The irectfet package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%. The IRF6603 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency C-C converters that power the latest generation of processors operating at higher frequencies. The IRF6603 has been optimized for parameters that are critical in synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6603 offers particularly low Rds(on) and high Cdv/ dt immunity for synchronous FET applications. Absolute Maximum Ratings Parameter Max. Units V S rain-to-source Voltage 30 V V GS Gate-to-Source Voltage 20/-12 T A = 25 C Continuous rain Current, V 10V f 27 A T A = 70 C Continuous rain Current, V 10V f 22 T C = 25 C Continuous rain Current, V 10V i 92 I M Pulsed rain Current c 200 A = 25 C Power issipation f 3.6 A = 70 C Power issipation f 2.3 W C = 25 C Power issipation i 42 Linear erating Factor W/ C T J Operating Junction and -40 to 150 C T STG Storage Temperature Range Thermal Resistance Parameter Typ. Max. Units R θja Junction-to-Ambient fj 35 R θja Junction-to-Ambient gj 12.5 R θja Junction-to-Ambient hj 20 C/W R θjc Junction-to-Case ij 3.0 R θj-pcb Junction-to-PCB Mounted 1.0 Notes through ˆ are on page /22/05

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV SS rain-to-source Breakdown Voltage 30 V V GS = 0V, I = 250µA ΒV SS / T J Breakdown Voltage Temp. Coefficient 28 mv/ C Reference to 25 C, I = 1mA R S(on) Static rain-to-source On-Resistance mω V GS = 10V, I = 25A e V GS = 4.5V, I = 20A e V GS(th) Gate Threshold Voltage V V S = V GS, I = 250µA V GS(th) / TJ Gate Threshold Voltage Coefficient -6.3 mv/ C I SS rain-to-source Leakage Current 30 µa V S = 24V, V GS = 0V 50 µa V S = 30V, V GS = 0V V S = 24V, V GS = 0V, T J = 70 C I GSS Gate-to-Source Forward Leakage na V GS = 20V Gate-to-Source Reverse Leakage - V GS = -12V gfs Forward Transconductance 56 S V S = 15V, I = 20A Q g Total Gate Charge Q gs1 Pre-Vth Gate-to-Source Charge 15.6 V S = 15V Q gs2 Post-Vth Gate-to-Source Charge 5.2 nc V GS = 4.5V Q gd Gate-to-rain Charge 16.1 I = 20A Q godr Gate Charge Overdrive 11.1 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 21.3 Q oss Output Charge 28 nc V S = 16V, V GS = 0V R G Gate Resistance Ω t d(on) Turn-On elay Time 20 V = 15V, V GS = 4.5Ve t r Rise Time 9.9 I = 20A t d(off) Turn-Off elay Time 24 ns Clamped Inductive Load t f Fall Time 71 C iss Input Capacitance 6590 V GS = 0V C oss Output Capacitance 1250 pf V S = 15V C rss Reverse Transfer Capacitance 520 ƒ = 1.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 49 mj I AR Avalanche Currentc 20 A E AR Repetitive Avalanche Energy c 4.1 mj iode Characteristics Conditions Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 38 MOSFET symbol (Body iode) A showing the G I SM Pulsed Source Current 200 integral reverse S (Body iode)c p-n junction diode. V S iode Forward Voltage V T J = 25 C, I S = 20A, V GS = 0V e t rr Reverse Recovery Time ns T J = 25 C, I F = 20A Q rr Reverse Recovery Charge nc di/dt = A/µs e 2

3 I, rain-to-source Current (Α) I, rain-to-source Current (A) I, rain-to-source Current (A) IRF VGS TOP 10V 5.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V 0 VGS TOP 10V 5.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V V 20µs PULSE WITH Tj = 25 C V S, rain-to-source Voltage (V) 1 2.7V 20µs PULSE WITH Tj = 150 C V S, rain-to-source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I = 25A.00 T J = 150 C T J = 25 C 1.00 V S = 15V 20µs PULSE WITH V GS, Gate-to-Source Voltage (V) R S(on), rain-to-source On Resistance (Normalized) V GS = 10V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I, rain-to-source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTE C rss = C gd C oss = C ds C gd I = 20A V S = 15V 00 Ciss 4.0 Coss Crss V S, rain-to-source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. rain-to-source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0 0 OPERATION IN THIS AREA LIMITE BY R S (on) I S, Reverse rain Current (A) T = 150 J C 10 T = 25 J C 1 V GS= 0 V V S,Source-to-rain Voltage (V) Tc = 25 C Tj = 150 C Single Pulse µsec 1msec 10msec V S, rain-tosource Voltage (V) Fig 7. Typical Source-rain iode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I, rain Current (A) V GS(th) Gate threshold Voltage (V) IRF I = 250µA T C, Case Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum rain Current Vs. Case Temperature Fig 10. Threshold Voltage Vs. Temperature Thermal Response (Z thja ) = SINGLE PULSE (THERMAL RESPONSE) P M t 1 t 2 Notes: 1. uty factor = t 1 / t 2 2. Peak T J = P M x Z thja T A t 1, Rectangular Pulse uration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 5

6 R G V S 20V V GS tp L.U.T IAS 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp 15V RIVER - V A V (BR)SS E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I 8.9A 16A 20A Starting Tj, Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy Vs. rain Current I AS Fig 12b. Unclamped Inductive Waveforms V S L V - Current Regulator Same Type as.u.t. V GS Pulse Width < 1µs uty Factor < 0.1%.U.T 50KΩ 12V.2µF.3µF Fig 14a. Switching Time Test Circuit.U.T. V - S V S 90% V GS 3mA 10% I G I Current Sampling Resistors Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 V GS t d(on) t r t d(off) t f

7 -.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current river Gate rive Period P.W..U.T. I S Waveform Body iode Forward Current di/dt.u.t. V S Waveform iode Recovery dv/dt = P.W. Period V GS =10V V * R G dv/dt controlled by RG river same type as.u.t. I S controlled by uty Factor "".U.T. - evice Under Test V - Re-Applied Voltage Inductor Curent Body iode Forward rop Ripple 5% I S * V GS = 5V for Logic Level evices Fig 15. Peak iode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform 7

8 Power MOSFET Selection for Non-Isolated C/C Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f i g ( ) Q g V g f Q oss 2 V f in I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q1. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q1 turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8

9 irectfet Outline imension, MT Outline (Medium Size Can, T-esignation). Please see irectfet application note AN-1035 for all details regarding the assembly of irectfet. This includes all recommendations for stencil and substrate designs. COE A B C E F G H J K L M N P IMENSIONS METRIC IMPERIAL MIN MAX MIN MAX

10 irectfet Substrate and PCB Layout, MT Outline (MediumSize Can, T-esignation). Please see irectfet application note AN-1035 for all details regarding the assembly of irectfet. This includes all recommendations for stencil and substrate designs. G = GATE = RAIN S = SOURCE G S S irectfet Part Marking

11 irectfet Tape & Reel imension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6603). For 0 parts on 7" reel, order IRF6603TR1 REEL IMENSIONS STANAR OPTION (QTY 4800) TR1 OPTION (QTY 0) METRIC IMPERIAL METRIC IMPERIAL COE A B C E F G H MIN MAX MIN MAX MIN MAX MIN MAX Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.24mH R G = 25Ω, I AS = 20A. ƒ Pulse width 400µs; duty cycle 2%. Surface mounted on 1 in. square Cu board. Used double sided cooling, mounting pad. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. T C measured with thermal couple mounted to top (rain) of part. ˆ R θ is measured at T J of approximately 90 C. ata and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORL HEAQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information.12/

12 Note: For the most current drawings please refer to the IR website at: