V DSS R DS(on) max I D. 30V GS = 10V 13A. 100 P A = 25 C Power Dissipation 2.5 P A = 70 C Power Dissipation Linear Derating Factor

Transcription

1 pplications l Control FET for Notebook Processor Power l Control and Synchronous Rectifier MOSFET for Graphics Cards and POL Converters in Computing, Networking and Telecommunication Systems 8 S 2 7 S P IRF743Z HEXFET Power MOSFET V SS R S(on) max I 30V m:@v GS = V 3 Benefits l Ultra-Low Gate Impedance l Very Low R S(on) l Fully Characterized valanche Voltage and Current S G Top View SO-8 l % Tested for R G bsolute Maximum Ratings Parameter Max. Units V S rain-to-source Voltage 30 V V GS Gate-to-Source Voltage ± 20 T = 25 C Continuous rain Current, V V 3 T = 70 C Continuous rain Current, V V I M Pulsed rain Current c = 25 C Power issipation 2.5 W = 70 C Power issipation Linear erating Factor W/ C T J Operating Junction and -55 to 50 C Storage Temperature Range T STG Thermal Resistance Parameter Typ. Max. Units R θjl Junction-to-rain Lead 20 C/W R θj Junction-to-mbient f 50 Notes through are on page 6/30/05

2 IRF743Z T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV SS rain-to-source Breakdown Voltage 30 V V GS = 0V, I = 250µ ΒV SS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I = m R S(on) Static rain-to-source On-Resistance 8.0 mω V GS = V, I = 3 e.5 3 V GS = 4.5V, I = e V GS(th) Gate Threshold Voltage V V S = V GS, I = 250µ V GS(th) / T J Gate Threshold Voltage Coefficient -5.0 mv/ C I SS rain-to-source Leakage Current.0 µ V S = 24V, V GS = 0V 50 V S = 24V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage n V GS = 20V Gate-to-Source Reverse Leakage - V GS = -20V gfs Forward Transconductance 62 S V S = 5V, I = Q g Total Gate Charge Q gs Pre-Vth Gate-to-Source Charge 3.0 V S = 5V Q gs2 Post-Vth Gate-to-Source Charge.0 nc V GS = 4.5V Q gd Gate-to-rain Charge 3.0 I = Q godr Gate Charge Overdrive 2.5 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 4.0 Q oss Output Charge 5.6 nc V S = 5V, V GS = 0V R G Gate Resistance Ω t d(on) Turn-On elay Time 8.7 V = 6V, V GS = 4.5V t r Rise Time 6.3 I = t d(off) Turn-Off elay Time ns Clamped Inductive Load t f Fall Time 3.8 C iss Input Capacitance 2 V GS = 0V C oss Output Capacitance 270 pf V S = 5V C rss Reverse Transfer Capacitance 40 ƒ =.0MHz valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energy d 32 mj I R valanche Current c iode Characteristics Parameter Min. Typ. Max. Units Conditions Conditions I S Continuous Source Current 3. MOSFET symbol (Body iode) showing the I SM Pulsed Source Current integral reverse (Body iode)c p-n junction diode. V S iode Forward Voltage.0 V T J = 25 C, I S =, V GS = 0V e t rr Reverse Recovery Time ns T J = 25 C, I F =, V = 5V Q rr Reverse Recovery Charge 6 24 nc di/dt = /µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSL) 2

3 I, rain-to-source Current (Α) R S(on), rain-to-source On Resistance (Normalized) I, rain-to-source Current () I, rain-to-source Current () IRF743Z 0 VGS TOP V 8.0V 4.5V 4.0V 3.5V 3.0V 2.8V BOTTOM 2.5V 0 VGS TOP V 8.0V 4.5V 4.0V 3.5V 3.0V 2.8V BOTTOM 2.5V 2.5V 2.5V 0. 20µs PULSE WITH Tj = 25 C 0. V S, rain-to-source Voltage (V) 20µs PULSE WITH Tj = 50 C 0. V S, rain-to-source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I = 3 V GS = V T J = 50 C.5 T J = 25 C.0 V S = V 20µs PULSE WITH V GS, Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I S, Reverse rain Current () I, rain-to-source Current () C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF743Z 00 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTE C rss = C gd C oss = C ds C gd I = V S = 24V V S = 5V 8.0 C iss C oss 4.0 C rss V S, rain-to-source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. rain-to-source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERTION IN THIS RE LIMITE BY R S (on).00 T J = 50 C.00 µsec T.00 J = 25 C V GS = 0V V S, Source-to-rain Voltage (V) 0. T = 25 C Tj = 50 C Single Pulse msec msec 0 0 V S, rain-to-source Voltage (V) Fig 7. Typical Source-rain iode Forward Voltage Fig 8. Maximum Safe Operating rea 4

5 I, rain Current () V GS(th) Gate threshold Voltage (V) IRF743Z I = 250µ T, mbient Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum rain Current vs. mbient Temperature Fig. Threshold Voltage vs. Temperature Thermal Response ( Z thj ) = R R 2 R 3 R R 2 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri R 4 Ri ( C/W) τi (sec) R τ 4 τ 4 τ C τ SINGLE PULSE ( THERML RESPONSE ) P M t t Notes:. uty factor = t / t 2 2. Peak T = P x Z T J M thj E-006 E t, Rectangular Pulse uration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-mbient 5

6 E S, Single Pulse valanche Energy (mj) IRF743Z V S L 5V RIVER I TOP BOTTOM R G 20V V GS tp.u.t IS 0.0Ω - V Fig 2a. Unclamped Inductive Test Circuit tp V (BR)SS Starting T J, Junction Temperature ( C) Fig 2c. Maximum valanche Energy vs. rain Current I S Fig 2b. Unclamped Inductive Waveforms V S L V - Current Regulator Same Type as.u.t. V GS Pulse Width < µs uty Factor < 0.%.U.T 50KΩ 2V.2µF.3µF Fig 4a. Switching Time Test Circuit.U.T. V - S V S 90% V GS 3m I G I Current Sampling Resistors % V GS Fig 3. Gate Charge Test Circuit Fig 4b. Switching Time Waveforms 6 t d(on) t r t d(off) t f

7 IRF743Z -.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current river Gate rive Period P.W..U.T. I S Waveform Body iode Forward Current di/dt.u.t. V S Waveform iode Recovery dv/dt = P.W. Period V GS =V V * R G dv/dt controlled by RG river same type as.u.t. I S controlled by uty Factor "".U.T. - evice Under Test V - Re-pplied Voltage Inductor Curent Body iode Forward rop Ripple 5% I S * V GS = 5V for Logic Level evices Fig 5. Peak iode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 6. Gate Charge Waveform 7

8 IRF743Z Power MOSFET Selection for Non-Isolated C/C Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f i g ( ) Q g V g f Q oss 2 V f in I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. s Q turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs must be minimized to reduce the potential for Cdv/dt turn on. Figure : Q oss Characteristic 8

9 IRF743Z SO-8 Package etails E B H 0.25 [.0] X e IM INCHES MILLIME T ERS MIN MX MIN MX b c E e e H K L y BS IC.27 BS IC.025 BS IC BSIC e C y K x 45 8X b 0.25 [.0] C B SO-8 Part Marking 0. [.004] NOT ES:. IMENSIONING & TOLERNCING PER SME Y4.5M CONTROLLING IMENSION: MILLIMETER 3. IMENSIONS RE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEEC OUTLINE MS IMENSION OES NOT INCLUE MOL PROTRUSIONS. MOL PROTRUSIONS NOT TO EXCEE 0.5 [.006]. 6 IMENSION OES NOT INCLUE MOL PROTRUSIONS. MOL PROTRUSIONS NOT TO EXCEE 0.25 [.0]. 7 IMENSION IS THE LENGTH OF LE FOR SOLERING TO SUBSTRTE. 8X L 8X c [.255] 3X.27 [.050] FOOTPRINT 8X 0.72 [.028] 8X.78 [.070] EXMPLE: THIS IS N IRF7 (MOSFET) INTERNTIONL RECTIFIER LOGO XXXX F7 TE COE (YWW) P = ESIGNTES LE-FREE PROUCT (OPTIONL) Y = LST IGIT OF THE YER WW = WEEK = S S E MB LY S IT E COE LOT COE PRT NUMBER 9

10 IRF743Z SO-8 Tape and Reel imensions are shown in millimeters (inches) TERMINL NUMBER 2.3 (.484 ).7 (.46 ) 8. (.38 ) 7.9 (.32 ) FEE IRECTION NOTES:. CONTROLLING IMENSION : MILLIMETER. 2. LL IMENSIONS RE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EI-48 & EI (2.992) MX. NOTES :. CONTROLLING IMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EI-48 & EI (.566 ) 2.40 (.488 ) Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.62mH, R G = 25Ω, I S =. ƒ Pulse width 400µs; duty cycle 2%. When mounted on inch square copper board. ata and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORL HEQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) TC Fax: (3) Visit us at for sales contact information. 06/05