IRF6668PbF IRF6668TRPbF

Transcription

1 Typical R DS(on) (mω) V GS, Gate-to-Source Voltage (V) l RoHs Compliant l Lead-Free (Qualified up to 260 C Reflow) l pplication Specific MOSFETs l Ideal for High Performance Isolated Converter Primary Switch Socket l Optimized for Synchronous Rectification l Low Conduction Losses l High Cdv/dt Immunity l Low Profile (<0.7mm) l Dual Sided Cooling Compatible l Compatible with existing Surface Mount Techniques IRF6668PbF IRF6668TRPbF DirectFET Power MOSFET Typical values (unless otherwise specified) V DSS V GS R DS(on) 80V max ±20V max 2mΩ@ V PD Q g tot Q gd Q gs2 Q rr Q oss V gs(th) 22nC 7.8nC.6nC 40nC 2nC 4.0V pplicable DirectFET Outline and Substrate Outline (see p.7,8 for details) SQ SX ST MQ MX MT MZ DirectFET ISOMETRIC Description The IRF6668PbF combines the latest HEXFET Power MOSFET Silicon technology with the advanced DirectFET TM packaging to achieve the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques. pplication note N-35 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%. The IRF6668PbF is optimized for primary side bridge topologies in isolated DC-DC applications, for 48V(±%) or 36V-60V ETSI input voltage range systems. The IRF6668PbF is also ideal for secondary side synchronous rectification in regulated isolated DC-DC topologies. The reduced total losses in the device coupled with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability improvements, and makes this device ideal for high performance isolated DC-DC converters. bsolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 80 V V GS Gate-to-Source Voltage ±20 I T C = 25 C Continuous Drain Current, V V f 55 I T C = 70 C Continuous Drain Current, V V f 44 I DM Pulsed Drain Current g 70 E S Single Pulse valanche Energy h 24 mj I R valanche Currentg I D = I D = 2 MZ V DS = 64V V DS = 40V T J = 25 C T J = 25 C V GS, Gate -to -Source Voltage (V) Fig. Typical On-Resistance vs. Gate-to-Source Voltage Notes: Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. ƒ Surface mounted on in. square Cu board, steady state Q G, Total Gate Charge (nc) Fig 2. Total Gate Charge vs. Gate-to-Source Voltage T C measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.088mH, R G = 25Ω, I S = /28/06 2.0

2 IRF6668PbF T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 80 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = m R DS(on) Static Drain-to-Source On-Resistance 2 5 mω V GS = V, I D = 2 i V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 0µ V GS(th) / T J Gate Threshold Voltage Coefficient - mv/ C I DSS Drain-to-Source Leakage Current 20 µ V DS = 80V, V GS = 0V 250 V DS = 64V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 0 n V GS = 20V Gate-to-Source Reverse Leakage -0 V GS = -20V gfs Forward Transconductance 22 S V DS = V, I D = 2 Q g Total Gate Charge 22 3 Q gs Pre-Vth Gate-to-Source Charge 4.8 V DS = 40V Q gs2 Post-Vth Gate-to-Source Charge.6 nc V GS = V Q gd Gate-to-Drain Charge I D = 2 Q godr Gate Charge Overdrive 7.8 See Fig. 5 Q sw Switch Charge (Q gs2 Q gd ) 9.4 Q oss Output Charge 2 nc V DS = 6V, V GS = 0V R G(Internal) Gate Resistance.0 Ω t d(on) Turn-On Delay Time 9 V DD = 40V, V GS = Vi t r Rise Time 3 I D = 2 t d(off) Turn-Off Delay Time 7. ns R G = 6.2Ω t f Fall Time 23 See Fig. 6 & 7 C iss Input Capacitance 320 V GS = 0V C oss Output Capacitance 3 pf V DS = 25V C rss Reverse Transfer Capacitance 76 Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 8 (Body Diode) I SM Pulsed Source Current 70 (Body Diode)g V SD Diode Forward Voltage.3 V t rr Reverse Recovery Time 34 5 ns Q rr Reverse Recovery Charge nc Conditions V GS = 0V, I D = 250µ ƒ =.0MHz MOSFET symbol showing the integral reverse Conditions p-n junction diode. T J = 25 C, I S = 2, V GS = 0V i T J = 25 C, I F = 2 di/dt = 0/µs isee Fig. 8 Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400µs; duty cycle 2%. 2

3 bsolute Maximum Ratings IRF6668PbF Parameter Max. Units P = 25 C Power Dissipation e 2.8 W P = 70 C Power Dissipation e.8 P C = 25 C Power Dissipation f 89 T P Peak Soldering Temperature 270 C T J Operating Junction and -40 to 50 Storage Temperature Range T STG Thermal Resistance Parameter Typ. Max. Units R θj Junction-to-mbient em 45 R θj Junction-to-mbient km 2.5 R θj Junction-to-mbient lm 20 C/W R θjc Junction-to-Case fm.4 R θj-pcb Junction-to-PCB Mounted.0 Linear Derating Factor e W/ C D = 0.50 Thermal Response ( Z thjc ) SINGLE PULSE ( THERML RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc 0.00 E-006 E Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-mbient Notes: Used double sided cooling, mounting pad. Š Mounted on minimum footprint full size board with metalized back and with small clip heatsink. R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci= τi/ri t, Rectangular Pulse Duration (sec) τ C τ C Ri ( C/W) τi (sec) R θ is measured at T J of approximately 90 C. ƒ Surface mounted on in. square Cu Mounted to a PCB with Š Mounted on minimum (still air). small clip heatsink (still air) footprint full size board with metalized back and with small clip heatsink (still air) 3

4 C, Capacitance (pf) Typical R DS (on) ( mω) I D, Drain-to-Source Current () Typical R DS(on) (Normalized) I D, Drain-to-Source Current () I D, Drain-to-Source Current () IRF6668PbF 00 0 VGS TOP 5V V 8.0V 7.0V BOTTOM 6.0V 00 0 VGS TOP 5V V 8.0V 7.0V BOTTOM 6.0V 6.0V 6.0V 60µs PULSE WIDTH Tj = 25 C 0. V DS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics 60µs PULSE WIDTH Tj = 50 C 0. V DS, Drain-to-Source Voltage (V) Fig 5. Typical Output Characteristics 00 V DS = V 60µs PULSE WIDTH 2.0 I D = 2 V GS = V 0 T J = 50 C T J = 25 C T J = -40 C V GS, Gate-to-Source Voltage (V) Fig 6. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 7. Normalized On-Resistance vs. Temperature V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss Vgs = 7.0V Vgs = 8.0V Vgs = V Vgs = 5V T J = 25 C C oss 30 0 C rss V DS, Drain-to-Source Voltage (V) I D, Drain Current () Fig 8. Typical Capacitance vs.drain-to-source Voltage Fig 9. Typical On-Resistance vs. Drain Current 4

5 E S, Single Pulse valanche Energy (mj) I D, Typical V GS(th), Drain Current () Gate threshold Voltage (V) I SD, Reverse Drain Current () I D, Drain-to-Source Current () IRF6668PbF OPERTION IN THIS RE LIMITED BY R DS (on) 0 T J = 50 C T J = 25 C T J = -40 C 0 0µsec msec msec V GS = 0V V SD, Source-to-Drain Voltage (V) Fig. Typical Source-Drain Diode Forward Voltage Tc = 25 C Tj = 50 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig. Maximum Safe Operating rea I D = 0µ I D = 250µ I D =.0m I D = T C, Case Temperature ( C) Fig 2. Maximum Drain Current vs. Case Temperature T J, Temperature ( C ) Fig 3. Threshold Voltage vs. Temperature 0 80 I D TOP BOTTOM Starting T J, Junction Temperature ( C) Fig 4. Maximum valanche Energy vs. Drain Current 5

6 IRF6668PbF Current Regulator Same Type as D.U.T. Vds Id 2V.2µF 50KΩ.3µF Vgs D.U.T. V - DS V GS Vgs(th) 3m I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 5a. Gate Charge Test Circuit Fig 5b. Gate Charge Waveform V (BR)DSS 5V tp V DS L DRIVER R G V GS 20V tp D.U.T I S 0.0Ω - V DD I S Fig 6a. Unclamped Inductive Test Circuit Fig 6b. Unclamped Inductive Waveforms L D V DS V DD - V DS 90% D.U.T % V GS V GS Pulse Width < µs Duty Factor < 0.% t d(on) t r t d(off) t f Fig 7a. Switching Time Test Circuit Fig 7b. Switching Time Waveforms 6

7 IRF6668PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G di/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-pplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 8. Diode Reverse Recovery Test Circuit for N-Channel HEXFET Power MOSFETs DirectFET Substrate and PCB Layout, MZ Outline (Medium Size Can, Z-Designation). Please see DirectFET application note N-35 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. 7

8 IRF6668PbF DirectFET Outline Dimension, MZ Outline (Medium Size Can, Z-Designation). Please see DirectFET application note N-35 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. DirectFET Part Marking CODE B C D E F G H J K L M R P DIMENSIONS METRIC IMPERIL

9 DirectFET Tape & Reel Dimension (Showing component orientation). IRF6668PbF NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6668TRPBF). For 00 parts on 7" reel, order IRF6668TRPBF CODE B C D E F G H REEL DIMENSIONS STNDRD OPTION (QTY 4800) TR OPTION (QTY 00) METRIC IMPERIL METRIC IMPERIL LODED TPE FEED DIRECTION CODE B C D E F G H DIMENSIONS METRIC IMPERIL Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) TC Fax: (3) Visit us at for sales contact information.08/06 9

10 Note: For the most current drawings please refer to the IR website at: