Description Absolute Maximum Ratings Parameter Max. Units Thermal Resistance Parameter Typ. Max. Units

Transcription

1 l Logic-Level Gate Drive l dvanced Process Technology l Isolated Package l High Voltage Isolation = 2.5KVRMS l Sink to Lead Creepage Dist. = 4.8mm l Fully valanche Rated l Lead-Free Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G PD HEXFET Power MOSFET D S V DSS = 55V R DS(on) = 0.022Ω I D = 30 The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using TO-220 FULLPK a micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 30 I T C = C Continuous Drain Current, V V 22 I DM Pulsed Drain Current 60 P C = 25 C Power Dissipation 45 W Linear Derating Factor 0.3 W/ C V GS Gate-to-Source Voltage ± 6 V E S Single Pulse valanche Energy 2 mj I R valanche Current 25 E R Repetitive valanche Energy 4.5 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 screw lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 3.3 R θj Junction-to-mbient 65 C/W 6/23/04

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = m V GS = V, I D = 7 R DS(on) Static Drain-to-Source On-Resistance Ω V GS = 5.0V, I D = V GS = 4.0V, I D = 4 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance 2 S V DS = 25V, I D = 25 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage V GS = 6V n Gate-to-Source Reverse Leakage - V GS = -6V Q g Total Gate Charge 48 I D = 25 Q gs Gate-to-Source Charge 8.6 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 25 V GS = 5.0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time V DD = 28V t r Rise Time 84 I ns D = 25 t d(off) Turn-Off Delay Time 26 R G = 3.4Ω, V GS = 5.0V t f Fall Time 5 R D =.Ω, See Fig. Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 700 V GS = 0V C oss Output Capacitance 400 V DS = 25V pf C rss Reverse Transfer Capacitance 50 ƒ =.0MHz, See Fig. 5 C Drain to Sink Capacitance 2 ƒ =.0MHz Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I D S Continuous Source Current MOSFET symbol 30 (Body Diode) showing the I SM Pulsed Source Current integral reverse G 60 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 7, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 25 Q rr Reverse RecoveryCharge µc di/dt = /µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) D S Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) V DD = 5V, starting T J = 25 C, L = 470µH R G = 25Ω, I S = 25. (See Figure 2) ƒ I SD 25, di/dt 270/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. t=60s, ƒ=60hz Uses IRLZ44N data and test conditions

3 I D, Drain-to-Source Current () VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V I D, Drain-to-Source Current () VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH T J = 25 C 0. V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current () T = 25 C J T = 75 C J V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) I D = 4 V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 C, Capacitance (pf) 2800 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED 2400 C rss = Cgd C = C C C iss oss ds gd Coss 800 C rss V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I D = 25 V DS = 44V V DS = 28V FOR TEST CIRCUIT SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () T = 75 C J T = 25 C J I D, Drain Current () OPERTION IN THIS RE LIMITED BY RDS(on) µs µs ms V GS = 0V V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage T C = 25 C ms T J = 75 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating rea

5 I D, Drain Current () R G V GS 5.0V V DS Pulse Width µs Duty Factor 0. % R D D.U.T. Fig a. Switching Time Test Circuit - V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J= P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 L V DS D.U.T. R G V - DD 5.0 V I S t p 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM V DD = 25V Starting T J, Junction Temperature ( C) Fig 2c. Maximum valanche Energy Vs. Drain Current ID 7 25 V DS I S Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF 5.0 V Q GS Q GD D.U.T. V - DS V GS V G 3m Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS

8 TO-220 Full-Pak Package Outline Dimensions are shown in millimeters (inches) TO-220 Full-Pak Part Marking Information E XMP LE : T H IS IS N IR F I840G WITH SSEMBLY LOT CODE 3432 S S EMB LE D ON WW IN THE SSEMBLY LINE "K" Note: "P" in assembly line position indicates "Lead-Free" INT E R NT IONL R E CT IF IE R LOGO S S E M B L Y LOT CODE IR FI840G 924K PRT NUMBER DTE CODE YER 9 = 999 WE EK 24 LINE K Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) TC Fax: (3) Visit us at for sales contact information.06/04

9 Note: For the most current drawings please refer to the IR website at: