C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Transcription

1 l Logic-Level Gate Drive l dvanced Process Technology l Surface Mount (IRL2505S) l Low-profile through-hole (IRL2505L) l 175 C Operating Temperature l Fast Switching l Fully valanche Rated Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL2505L) is available for lowprofile applications. bsolute Maximum Ratings PD D IRL2505S/L HEXFET Power MOSFET 2 D Pak TO-262 V DSS = 55V R DS(on) = 0.008Ω I D = 104 Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10V 104 I T C = C Continuous Drain Current, V 10V 74 I DM Pulsed Drain Current 360 P = 25 C Power Dissipation 3.8 W P C = 25 C Power Dissipation 200 W Linear Derating Factor 1.3 W/ C V GS Gate-to-Source Voltage ±16 V E S Single Pulse valanche Energy 500 mj I R valanche Current 54 E R Repetitive valanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 C/W R θj Junction-to-mbient ( PCB Mounted,steady-state)** 40 G D S 5/12/98

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1m V GS = 10V, I D = 54 R DS(on) Static Drain-to-Source On-Resistance Ω V GS = 5.0V, I D = V GS = 4.0V, I D = 45 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance 59 S V DS = 25V, I D = 54 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage V GS = 16V n Gate-to-Source Reverse Leakage - V GS = -16V Q g Total Gate Charge 130 I D = 54 Q gs Gate-to-Source Charge 25 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 67 V GS = 5.0V, See Fig. 6 and 13 t d(on) Turn-On Delay Time 12 V DD = 28V t r Rise Time 160 I D = 54 ns t d(off) Turn-Off Delay Time 43 R G = 1.3Ω, V GS = 5.0V t f Fall Time 84 R D = 0.50Ω, See Fig. 10 L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 5000 V GS = 0V C oss Output Capacitance 1 pf V DS = 25V C rss Reverse Transfer Capacitance 390 ƒ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 104 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 360 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 54, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 54 Q rr Reverse Recovery Charge nc di/dt = /µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) V DD = 25V, starting T J = 25 C, L = 240µH R G = 25Ω, I S = 54. (See Figure 12) ƒ I SD 54, di/dt 230/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2%. Uses IRL2505 data and test conditions Caculated continuous current based on maximum allowable junction temperature;for recommended current-handling of the package refer to Design Tip # 93-4 ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #N-994.

3 I D, Drain-to-Source Current () 10 VGS TOP 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE W IDTH 1 T J = 25 C V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current () 10 VGS TOP 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE W IDTH 1 T J = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current () 10 V DS= 25V 20µs PULSE WIDTH V GS T = 25 C J T = 175 C J, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics R DS(on), Drain-to-Source On Resistance (N orm alized) I D = 90 V GS = 10V T J, Junction Temperature ( C) Fig 4. Normalized On-Resistance Vs. Temperature

4 C, Capacitance (pf) C iss C oss C rss V GS = 0V, f = 1MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd V DS, Drain-to-Source Voltage (V) V, Gate-to-Source Voltage (V) GS I D = 54 V DS = 44V V DS = 28V FOR TEST CIRCUIT 0 SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERTION IN THIS RE LIMITED BY RDS(on) I SD, Reverse Drain Current () T = 175 C J T = 25 C J I D, Drain Current () 10 10µs µs 1ms 10ms V GS = 0V V SD, Source-to-Drain Voltage (V) T C = 25 C T J = 175 C 1 Single P u lse 1 10 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea

5 120 LIMITED BY PCKGE R G V GS D.U.T. - V DD I D, Drain Current () Fig 10a. Switching Time Test Circuit V DS 90% 5.0V Pulse Width 1 µs Duty Factor 0.1 % T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 1 Thermal Response (Z thjc ) 0.1 D = t SINGLE PULSE t (THERML RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc TC t 1, Rectangular Pulse Duration (sec) PDM Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 L V DS D.U.T. R G V - DD 10 V I S t p 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM V DD = 25V Starting T J, Junction Temperature ( C) ID V DS I S Fig 12b. Unclamped Inductive Waveforms Fig 12c. Maximum valanche Energy Vs. Drain Current Current Regulator Same Type as D.U.T. 50KΩ 10 V Q GS Q G Q GD 12V.2µF.3µF D.U.T. V - DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit IRL2505S/L D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS

8 D 2 Pak Package Outline 1.40 (.055) M X (.415) (.405) (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) REF (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) REF (.010) M B M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS FTER SOLDER DIP. 2 DIMENSIONING & TOLERNCING PER NSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HETSINK & LED DIMENSIONS DO NOT INCLUDE BURRS. LED SSIGNMENTS 1 - GTE 2 - DRIN 3 - SOURCE 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.) 2X Part Marking Information D 2 Pak INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE F530S B 1M PRT NUMBER DTE CODE (YYW W ) YY = YER WW = WEEK

9 Package Outline TO-262 Outline Part Marking Information TO-262

10 Tape & Reel Information D 2 Pak TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) (.457) (.449) (.609) (.601) (.957) (.941) TRL (.429) (.421) (.634) (.626) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MX (2.362) MIN. NOTES : 1. COMFORMS TO EI CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLNGE OUTER EDGE (1.039) (.961) (1.197) MX. 4 WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CND: 7321 Victoria Park ve., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) IR GERMNY: Saalburgstrasse 157, Bad Homburg Tel: IR ITLY: Via Liguria 49, 71 Borgaro, Torino Tel: IR FR EST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: IR SOUTHEST SI: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: Data and specifications subject to change without notice. 5/98

11 Note: For the most current drawings please refer to the IR website at: