Description Absolute Maximum Ratings Parameter Max. Units Thermal Resistance Parameter Min. Typ. Max. Units

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1 Logic-Leve Gate Drive dvanced Process Technoogy Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fuy vaanche Rated Lead-Free Description Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve the owest possibe on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient device for use in a wide variety of appications. G PD IRLZ34NPbF HEXFET Power MOSFET D S V DSS = 55V R DS(on) = 0.035Ω I D = 30 The TO-220 package is universay preferred for a commercia-industria appications at power dissipation eves to approximatey 50 watts. The ow therma resistance and ow package cost of the TO-220 contribute to its wide acceptance throughout the industry. bsoute Maximum Ratings TO-220B Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 30 I T C = 0 C Continuous Drain Current, V V 2 I DM Pused Drain Current P C = 25 C Power Dissipation 68 W Linear Derating Factor 0.45 W/ C V GS Gate-to-Source Votage ±6 V E S Singe Puse vaanche Energy mj I R vaanche Current 6 E R Repetitive vaanche Energy 6.8 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Sodering Temperature, for seconds 300 (.6mm from case) Mounting torque, 6-32 or M3 screw. bf in (.N m) Therma Resistance Parameter Min. Typ. Max. Units R θjc Junction-to-Case 2.2 R θcs Case-to-Sink, Fat, Greased Surface 0.50 C/W R θj Junction-to-mbient 62 //03

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Votage Temp. Coefficient V/ C Reference to 25 C, I D = m V GS = V, I D = 6 R DS(on) Static Drain-to-Source On-Resistance Ω V GS = 5.0V, I D = V GS = 4.0V, I D = 4 V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µ g fs Forward Transconductance S V DS = 25V, I D = 6 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 6V n Gate-to-Source Reverse Leakage -0 V GS = -6V Q g Tota Gate Charge 25 I D = 6 Q gs Gate-to-Source Charge 5.2 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge 4 V GS = 5.0V, See Fig. 6 and 3 t d(on) Turn-On Deay Time 8.9 V DD = 28V t r Rise Time 0 I D = 6 ns t d(off) Turn-Off Deay Time 2 R G = 6.5Ω, V GS = 5.0V t f Fa Time 29 R D =.8Ω, See Fig. Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh from package L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 880 V GS = 0V C oss Output Capacitance 220 pf V DS = 25V C rss Reverse Transfer Capacitance 94 ƒ =.0MHz, See Fig. 5 G D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbo 30 (Body Diode) showing the G I SM Pused Source Current integra reverse (Body Diode) p-n junction diode. V SD Diode Forward Votage.3 V T J = 25 C, I S = 6, V GS = 0V t rr Reverse Recovery Time 76 ns T J = 25 C, I F = 6 Q rr Reverse RecoveryCharge nc di/dt = 0/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) D S Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L = 6µH R G = 25Ω, I S = 6. (See Figure 2) ƒ I SD 6, di/dt 270/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%.

3 I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH 0. T J = 75 C 0. 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J T = 75 C J V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) I D = 27 V GS = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature

4 C, Capacitance (pf) 400 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED 200 C rss = Cgd C iss C oss = C ds Cgd C oss Crss V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) I D = 6 V DS = 44V V DS = 28V FOR TEST CIRCUIT SEE FIGURE Q, Tota Gate Charge (nc) G Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J V GS = 0V V SD, Source-to-Drain Votage (V) I D, Drain Current () 00 OPERTION IN THIS RE LIMITED BY RDS(on) 0 µs 0µs ms T C = 25 C T J = 75 C ms Singe Puse 0 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating rea

5 40 V DS R D I D, Drain Current () T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig a. Switching Time Test Circuit V DS 90% R G V GS 5.0V Puse Width µs Duty Factor 0. % D.U.T. % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms - V DD Therma Response (Z thjc ) 0. D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t Peak T J= P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case

6 L V DS D.U.T. R G V - DD 5.0 V I S t p 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS t p E S, Singe Puse vaanche Energy (mj) I D TOP 6.6 BOTTOM 6 V DD = 25V Starting T J, Junction Temperature ( C) V DS V DD Fig 2c. Maximum vaanche Energy Vs. Drain Current I S Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF 5.0 V Q GS Q GD D.U.T. V - DS V GS V G 3m Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFETS

8 TO-220B Package Outine Dimensions are shown in miimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) (.255) 6. (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LED SSIGNMENTS LED SSIGNMENTS HEXFET IGBTs, CoPCK - GTE - GTE 2 - DRIN - GTE 2- DRIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRIN 3- EMITTER 4- DRIN 4- COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.0) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) DIMENSIONING & TOLERNCING PER NSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-220B. 2 CONTROLLING DIMENSION : INCH 4 HETSINK & LED MESUREMENTS DO NOT INCLUDE BURRS. TO-220B Part Marking Information EXMPLE: T HIS IS N IRF LOT CODE 789 S S EMBLED ON WW 9, 997 IN THE SSEMBLY LINE "C" Note: "P" in assemby ine position indicates "Lead-Free" INT ERNT IONL RE CT IFIER LOGO S S E MB L Y LOT CODE PRT NUMBER DTE CODE YER 7 = 997 WEEK 9 LINE C Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, US Te: (3) TC Fax: (3) Visit us at for saes contact information./03

9 Note: For the most current drawings pease refer to the IR website at:

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