PRELIMINARY. C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 dvanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fully valanche Rated PRELIMINRY PD IRFP064N HEXFET Power MOSFET V DSS = 55V R DS(on) = 0.008Ω I D = 98 Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. The TO-247 is similar but superior to the earlier TO-28 package because of its isolated mounting hole. bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 98 I T C = C Continuous Drain Current, V V 69 I DM Pulsed Drain Current 390 P C = 25 C Power Dissipation 50 W Linear Derating Factor.0 W/ C V GS Gate-to-Source Voltage ± 20 V E S Single Pulse valanche Energy 480 mj I R valanche Current 59 E R Repetitive valanche Energy 5 mj dv/dt Peak Diode Recovery dv/dt 4.0 V/ns T J Operating Junction and -55 to + 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 srew lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.0 R θcs Case-to-Sink, Flat, Greased Surface 0.24 C/W R θj Junction-to-mbient 40

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = m R DS(on) Static Drain-to-Source On-Resistance Ω V GS = V, I D = 59 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance 42 S V DS = 25V, I D = 59 I DSS Drain-to-Source Leakage Current 25 V µ DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage V GS = 20V n Gate-to-Source Reverse Leakage - V GS = -20V Q g Total Gate Charge 70 I D = 59 Q gs Gate-to-Source Charge 32 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 74 V GS = V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 4 V DD = 28V t r Rise Time I D = 59 ns t d(off) Turn-Off Delay Time 43 R G = 2.5Ω t f Fall Time 70 R D = 0.39Ω, See Fig. Between lead, L D Internal Drain Inductance 5.0 6mm (0.25in.) nh from package L S Internal Source Inductance 3 and center of die contact C iss Input Capacitance 4000 V GS = 0V C oss Output Capacitance 300 pf V DS = 25V C rss Reverse Transfer Capacitance 480 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 98 (Body Diode) showing the I SM Pulsed Source Current integral reverse 390 (Body Diode) p-n junction diode. V SD Diode Forward Voltage.3 V T J = 25 C, I S = 59, V GS = 0V t rr Reverse Recovery Time 70 ns T J = 25 C, I F = 59 Q rr Reverse Recovery Charge nc di/dt = /µs Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L = 90µH R G = 25Ω, I S = 59. (See Figure 2) I SD 59, di/dt 290/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4 Uses IRF3205 data and test conditions.

3 I, Drain-to-Source Current () D VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T C = 25 C 0. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics, T J = 25 o C I, Drain-to-Source Current () D VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T C = 75 C 0. V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics, T J = 75 o C I D, Drain-to-Source Current () T = 25 C J T = 75 C J V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) I D = 98 V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 C, Capacitance (pf) 8000 V GS = 0V, f = MHz 7000 C iss = C gs + C gd, C ds SHORTED C rss = Cgd C oss = C ds + Cgd 6000 C iss C oss C rss 0 V DS, Drain-to-Source Voltage (V) V, Gate-to-Source Voltage (V) GS I D = 59 V DS = 44V V DS = 28V V DS = V FOR TEST CIRCUIT SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () T = 75 C J T = 25 C J I D, Drain Current () OPERTION IN THIS RE LIMITED BY RDS(on) µs µs ms ms V GS = 0V V SD, Source-to-Drain Voltage (V) T C = 25 C T J = 75 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea

5 LIMITED BY PCKGE V GS V DS R D D.U.T. R G 80 V DD I D, Drain Current (mps) V Pulse Width µs Duty Factor 0. % Fig a. Switching Time Test Circuit T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = Notes:. D uty factor D = t / t 2 SINGLE PULSE 0.0 (THERML RESPONSE) 2. P eak T J = P D M x Z th JC + T C t, Rectangular Pulse Duration (sec) PD M t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 V Fig 2a. Unclamped Inductive Test Circuit E S, Single Pulse valanche Energy (mj) ID TOP BOTTOM 59 V DD = 25V Starting T J, Junction Temperature ( C) Fig 2b. Unclamped Inductive Waveforms Fig 2c. Maximum valanche Energy Vs. Drain Current V Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD * * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS

8 Package Outline TO-247C Outline Dimensions are shown in millimeters (inches) 5.90 (.626) 5.30 (.602) - B (.43) 3.55 (.40) 0.25 (.0) M 5.50 (.27) D B M - D (.209) 4.70 (.85) 2.50 (.089).50 (.059) (.800) 9.70 (.775) 4.80 (.583) 4.20 (.559) 2 3 2X - C (.70) 3.70 (.45) 5.50 (.27) 4.50 (.77) NOTES: DIMENSIONING & TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-247-C (.094) 2.00 (.079) 2X 5.45 (.25) 2X 3X 3.40 (.33) 3.00 (.8).40 (.056).00 (.039) 0.25 (.0) M C S 3X 0.80 (.03) 0.40 (.06) 2.60 (.2) 2.20 (.087) LED SSIGNMENTS - GTE 2 - DRIN 3 - SOURCE 4 - DRIN Part Marking Information TO-247C EXMPLE : THIS IS N IRFPE30 WITH SSEMBLY LOT CODE 3Q INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFPE30 3Q 9302 PRT NUMBER DTE CODE (YYWW) YY = YER WW WEEK WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 2Z8, Tel: (905) IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: IR ITLY: Via Liguria 49, 7 Borgaro, Torino Tel: IR FR EST: K&H Bldg., 2F, Nishi-Ikeburo 3-Chome, Toshima-Ku, Tokyo, Japan 7 Tel: IR SOUTHEST SI: 35 Outram Road, #-02 Tan Boon Liat Building, Singapore 036 Tel: Data and specifications subject to change without notice. 2/96

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