SMPS MOSFET. V DSS Rds(on) max I D

Transcription

1 SMPS MOSFET PD 980 pplications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching l High Voltage Isolation = 2.5KVRMS Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, valanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and valanche Voltage and Current l Effective Coss specified ( See N 00) HEXFET Power MOSFET V DSS Rds(on) max I D 500V 0.52Ω 6.6 TO220 FULLPK G D S bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V 6.6 I T C = 00 C Continuous Drain Current, V 0V 4.2 I DM Pulsed Drain Current 44 P C = 25 C Power Dissipation 60 W Linear Derating Factor 0.48 W/ C V GS GatetoSource Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 6.9 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torqe, 632 or M3 screw 0 lbf in (.N m) pplicable Off Line SMPS Topologies: l Two Transistor Forward l Half & Full Bridge Convertors l Power Factor Correction Boost Notes through are on page 8 6/5/99

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 500 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.6 V/ C Reference to 25 C, I D = m R DS(on) Static DraintoSource OnResistance 0.52 Ω V GS = 0V, I D = 4.0 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ I DSS DraintoSource Leakage Current 25 V µ DS = 500V, V GS = 0V 250 V DS = 400V, V GS = 0V, T J = 25 C I GSS GatetoSource Forward Leakage 00 V GS = 30V n GatetoSource Reverse Leakage 00 V GS = 30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 6. S V DS = 50V, I D = 6.6 Q g Total Gate Charge 52 I D = Q gs GatetoSource Charge 3 nc V DS = 400V Q gd GatetoDrain ("Miller") Charge 8 V GS = 0V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 4 V DD = 250V t r Rise Time 35 ns I D = t d(off) TurnOff Delay Time 32 R G = 9.Ω t f Fall Time 28 R D = 22Ω,See Fig. 0 C iss Input Capacitance 423 V GS = 0V C oss Output Capacitance 208 V DS = 25V C rss Reverse Transfer Capacitance 8. pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 2000 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 55 V GS = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 97 V GS = 0V, V DS = 0V to 400V valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energy 275 mj I R valanche Current E R Repetitive valanche Energy 6.0 mj Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 2. R θj Junctiontombient 65 C/W Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 6.6 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 44 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S =, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = Q rr Reverse RecoveryCharge µc di/dt = 00/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) 2

3 I D, DraintoSource Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D, DraintoSource Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH 4.5V T J = 50 C 0 00 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current () 00 0 T = 50 J C T J = 25 C V DS= 00V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 3.0 I D = V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature 3

4 C, Capacitance (pf) C iss C oss C rss V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I = D 6.6 V DS = 400V V DS = 250V V DS = 00V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage OPERTION IN THIS RE LIMITED BY R DS(on) I SD, Reverse Drain Current () 0 T J = 50 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Voltage (V) I D, Drain Current () us 00us ms 0ms TC = 25 C TJ = 50 C Single Pulse V DS, DraintoSource Voltage (V) 4 Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating rea

5 7.0 V DS R D I D, Drain Current () Fig 0a. Switching Time Test Circuit V DS 90% R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms 0 Thermal Response (Z thjc ) D = PDM 0. t t2 SINGLE PULSE Notes: (THERML RESPONSE). Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) 5

6 Fig 2a. Unclamped Inductive Test Circuit I S R G V DS 20V tp tp L D.U.T I S 0.0Ω V (BR)DSS Fig 2b. Unclamped Inductive Waveforms Q G 5V DRIVER V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM I D Starting T, Junction Temperature ( J C) Fig 2c. Maximum valanche Energy Vs. Drain Current 0 V Q GS Q GD 660 V G 2V V GS Current Regulator Same Type as D.U.T..2µF 50KΩ 3m.3µF Charge Fig 3a. Basic Gate Charge Waveform D.U.T. V DS V DSav, valanche Voltage (V) I av, valanche Current () I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6 Fig 2d. Typical DraintoSource Voltage Vs. valanche Current

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Repplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For NChannel HEXFETS 7

8 Package Outline TO220 Fullpak Outline Dimensions are shown in millimeters (inches) 6.00 (.630) 5.80 (.622) 3.70 (.540) 3.50 (.530) 0.60 (.47) 0.40 (.409) (.33) ø 3.0 (.23) 3.70 (.45) 3.20 (.26).5 (.045) MIN (.30) 3.0 (.22) B 4.80 (.89) 4.60 (.8) 7.0 (.280) 6.70 (.263) 2.80 (.0) 2.60 (.02) LED SSIGNMENTS G TE 2 DR IN 3 SO UR CE NOTES: DIMENSIONING & TOLERNCING PE R NS I Y4.5M, CONTROLLING DIMENSION: INCH. C D 2.54 (.00) 2X Part Marking Information TO220 Fullpak EXMPLE : 3X.40 (.055).05 (.042) 0.90 (.035) 3X 0.70 (.028) THIS IS N IRFI840G W ITH SSEMBLY LOT CODE E40 Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 4.5mH R G = 25Ω, I S =. (See Figure 2) ƒ I SD, di/dt 40/µs, V DD V (BR)DSS, T J 50 C 0.25 (.00) M M B INTERNTIONL R E CT IF IER LO GO SSEMBLY LO T CO DE 0.48 (.09) 3X 0.44 (.07) 2.85 (.2) 2.65 (.04) IRFI840G E Pulse width 300µs; duty cycle 2%. MINIMUM CREEPGE DISTNCE BETW EEN BCD = 4.80 (.89) PRT NUMBER DTE CODE (YYW W ) YY = YER WW = WEEK C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Uses IRFBN50 data and test conditions t=60s,f=60hz B