SMPS MOSFET. V DSS R DS(on) max I D

Transcription

1 pplications l Switch Mode Power Supply (SMPS) l Uninterruptible Power Supply l High Speed Power Switching l High Voltage Isolation = 2.5KVRMS Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, valanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and valanche Voltage and Current SMPS MOSFET IRFIB5N65 HEXFET Power MOSFET V DSS R DS(on) max I D 650V 0.93Ω 5. TO220 FullPak PD986B G D S bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V 5. I T C = 00 C Continuous Drain Current, V 0V 3.2 I DM Pulsed Drain Current 2 P C = 25 C Power Dissipation 60 W Linear Derating Factor 0.48 W/ C V GS GatetoSource Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 2.8 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torqe, 632 or M3 screw 0 lbf in (.N m) Typical SMPS Topologies l Single Transistor Flyback l Single Transistor Forward Notes through are on page 8 6/2/00

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 650 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.67 V/ C Reference to 25 C, I D = m R DS(on) Static DraintoSource OnResistance 0.93 Ω V GS = 0V, I D = 3.. V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ I DSS DraintoSource Leakage Current 25 V µ DS = 650V, V GS = 0V 250 V DS = 520V, V GS = 0V, T J = 25 C I GSS GatetoSource Forward Leakage 00 V GS = 30V n GatetoSource Reverse Leakage 00 V GS = 30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 3.9 S V DS = 50V, I D = 3. Q g Total Gate Charge 48 I D = 5.2 Q gs GatetoSource Charge 2 nc V DS = 400V Q gd GatetoDrain ("Miller") Charge 9 V GS = 0V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 4 V DD = 325V t r Rise Time 20 ns I D = 5.2 t d(off) TurnOff Delay Time 34 R G = 9.Ω t f Fall Time 8 R D = 62Ω,See Fig. 0 C iss Input Capacitance 47 V GS = 0V C oss Output Capacitance 77 V DS = 25V C rss Reverse Transfer Capacitance 7.0 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 92 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 48 V GS = 0V, V DS = 520V, ƒ =.0MHz C oss eff. Effective Output Capacitance 84 V GS = 0V, V DS = 0V to 520V valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energy 325 mj I R valanche Current 5.2 E R Repetitive valanche Energy 6 mj Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 2. R θj Junctiontombient 65 C/W Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 5.2 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 2 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = 5.2, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 5.2 Q rr Reverse RecoveryCharge µc di/dt = 00/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) 2

3 I D, DraintoSource Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D, DraintoSource Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 4.5V T J = 25 C V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH T J = 50 C V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current () 00 0 T = 50 J C T J = 25 C V DS= 00V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 3.0 I D = V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature 3

4 C, Capacitance (pf) V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss C oss C rss V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I = D 5.2 V DS = 400V 520V V DS = 325V V DS = 30V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage OPERTION IN THIS RE LIMITED BY R DS(on) I SD, Reverse Drain Current () 0 T J = 50 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Voltage (V) I D, Drain Current () 0 0us 00us ms 0ms TC = 25 C TJ = 50 C Single Pulse V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating rea 4

5 6.0 V DS R D I D, Drain Current () R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. Fig 0a. Switching Time Test Circuit V DD.0 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms 0 Thermal Response (Z thjc ) D = PDM t 0.02 t2 0.0 Notes: SINGLE PULSE (THERML RESPONSE). Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase 5

6 R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T I S 0.0Ω V (BR)DSS 5V DRIVER V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM I D Starting T, Junction Temperature ( J C) I S Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum valanche Energy Vs. Drain Current 0 V Q GS Q GD 800 V G 2V Current Regulator Same Type as D.U.T..2µF 50KΩ.3µF Charge Fig 3a. Basic Gate Charge Waveform V DSav, valanche Voltage (V) V GS 3m D.U.T. V DS I av, valanche Current () I G I D Current Sampling Resistors Fig 2d. Typical DraintoSource Voltage Fig 3b. Gate Charge Test Circuit Vs. valanche Current 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Repplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For NChannel HEXFET Power MOSFETs 7

8 TO220 FullPak Package Outline Dimensions are shown in millimeters (inches) 6.00 (.630) 5.80 (.622) 0.60 (.47) 0.40 (.409) (.33) ø 3.0 (.23) 3.70 (.45) 3.20 (.26).5 (.045) MIN (.30) 3.0 (.22) 4.80 (.89) 4.60 (.8) 7.0 (.280) 6.70 (.263) 2.80 (.0) 2.60 (.02) LED SSIGNMENTS G T E 2 D R IN 3 S OU R CE NOTES: DIMENSIONING & TOLERNCING PE R NS I Y 4.5M, CONTROLLING DIMENSION: INCH (.540) 3.50 (.530) B C D 3X.40 (.055).05 (.042) 2.54 (.00) 2X 0.90 (.035) 3X 0.70 (.028) 0.25 (.00) M M B TO220 FullPak Part Marking Information 0.48 (.09) 3X 0.44 (.07) 2.85 (.2) 2.65 (.04) MINIMUM CREEPGE DISTNCE BETW EEN BCD = 4.80 (.89) B EXM PLE : TH IS IS N IRFI840G W ITH SSEMBLY LOT CODE E40 Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ) Starting T J = 25 C, L = 24mH R G = 25Ω, I S = 5.2. (See Figure 2) ƒ I SD 5.2, di/dt 90/µs, V DD V (BR)DSS, T J 50 C INTERNTIONL R EC TIF IER LO G O SSEMBLY LOT CO DE IRFI840G E Pulse width 300µs; duty cycle 2%. PRT NUMBER DTE CODE (YYW W ) YY = YER W W = W EEK C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS t=60s, f=60hz IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (30) IR EUROPEN REGIONL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: 44 (0) IR CND: 5 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: 49 (0) IR ITLY: Via Liguria 49, 007 Borgaro, Torino Tel: IR JPN: K&H Bldg., 2F, 304 NishiIkebukuro 3Chome, ToshimaKu, Tokyo 7 Tel: 8 (0) IR SOUTHEST SI: Kim Seng Promenade, Great World City West Tower, 3, Singapore Tel: 65 (0) IR TIWN:6 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 0673 Tel: 886(0) Data and specifications subject to change without notice. 6/00 8