A I DM Pulsed Drain Current 10 P C = 25 C Power Dissipation 2.0

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1 l Adavanced Process Technology l Ultra Low On-Resistance l Dual N-Channel MOSFET l Surface Mount l Available in Tape & Reel l Dynamic dv/dt Rating l Fast Switching Description Fourth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and dual-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques. Power dissipation of greater than 0.8W is possible in a typical PCB mount application. S1 G1 S2 G2 PD B IRF7103 HEXFET Power MOSFET D1 D1 D2 D2 V DSS = 50V R DS(on) = 0.130Ω I D = 3.0A Top View SO-8 Absolute Maximum Ratings Parameter Max. Units I T A = 25 C Continuous Drain Current, V 10V 3.0 I T A = 70 C Continuous Drain Current, V 10V 2.3 A I DM Pulsed Drain Current 10 P C = 25 C Power Dissipation 2.0 W Linear Derating Factor W/ C V GS Gate-to-Source Voltage ± 20 V dv/dt Peak Diode Recovery dv/dt 4.5 V/nS T J, T STG Junction and Storage Temperature Range -55 to 150 C Thermal Resistance Ratings Parameter Min. Typ. Max. Units R θja Maximum Junction-to-Ambient 62.5 C/W 8/25/97

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 50 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA R DS(ON) Static Drain-to-Source On-Resistance V GS = 10V, I D = 3.0A ƒ Ω V GS = 4.5V, I D = 1.5A ƒ V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA g fs Forward Transconductance 3.8 S V DS = 15V, I D = 3.0A ƒ I DSS Drain-to-Source Leakage Current 2.0 V DS = 40V, V GS = 0V µa 25 V DS = 40V, V GS = 0V, T J = 55 C Gate-to-Source Forward Leakage 100 V GS = 20V I GSS na Gate-to-Source Reverse Leakage -100 V GS = - 20V Q g Total Gate Charge I D = 2.0A Q gs Gate-to-Source Charge 1.2 nc V DS = 25V Q gd Gate-to-Drain ("Miller") Charge 3.5 V GS = 10V ƒ t d(on) Turn-On Delay Time V DD = 25V t r Rise Time I D = 1.0A ns t d(off) Turn-Off Delay Time R G = 6.0Ω t f Fall Time R D = 25Ω ƒ L D Internal Drain Inductance 4.0 Between lead,6mm(0.25in.) nh G from package and center L S Internal Source Inductance 6.0 of die contact C iss Input Capacitance 290 V GS = 0V C oss Output Capacitance 140 pf V DS = 25V C rss Reverse Transfer Capacitance 37 ƒ = 1.0MHz D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 2.0 (Body Diode) showing the A I SM Pulsed Source Current integral reverse G 12 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.2 V T J = 25 C, I S = 1.5A, V GS = 0V ƒ t rr Reverse Recovery Time ns T J = 25 C, I F = 1.5A Q rr Reverse RecoveryCharge nc di/dt = 100A/µs ƒ t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ƒ Pulse width 300µs; duty cycle 2%. I SD 1.8A, di/dt 90A/µs, V DD V (BR)DSS, T J 150 C Surface mounted on FR-4 board, t 10sec.

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5 V DS R D R G V GS D.U.T. - V DD 10V Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit V DS 90% 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 100 Thermal Response (Z thja ) 10 1 D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1/ t 2 2. Peak T J = P DM x Z thja TA t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

6 Current Regulator Same Type as D.U.T. 10V Q GS Q G Q GD 12V.2µF 50KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 12a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 12b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * VGS = 5V for Logic Level Devices Fig 13. For N-Channel HEXFETS

8 Package Outline SO8 Outline 5 E - A - D - B H 0.25 (.010) M A M e 6X e1 K x 45 θ A - C (.004) L 6 B 8X A1 8X 0.25 (.010) M C A S B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M CONTROLLING DIMENSION : INCH. 3. DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES). 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA. 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS MOLD PROTRUSIONS NOT TO EXCEED 0.25 (.006). 6 DIMENSIONS IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.. C 8X INCHES MILLIMETERS DIM MIN MAX MIN MAX A A B C D E e.050 BASIC 1.27 BASIC e1.025 BASIC BASIC H K L θ RECOMMENDED FOOTPRINT 6.46 (.255 ) 1.27 (.050 ) 3X 0.72 (.028 ) 8X 1.78 (.070) 8X Part Marking Information SO8 EXAMPLE : THIS IS AN IRF7101 INTERNATIONAL RECTIFIER LOGO F7101 TOP 312 DATE CODE (YWW) Y = LAST DIGIT OF THE YEAR WW = WEEK PART NUMBER W AFER LOT CODE (LAST 4 DIGITS) XXXX BOTTOM

9 Tape & Reel Information SO8 Dimensions are shown in millimeters (inches) IRF7103 TERMINAL NUMBER (.484 ) 11.7 (.461 ) 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOW N IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA (12.992) M A X. NOTES : 1. CONTRO LLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA (.566 ) (.488 ) WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) IR GERMANY: Saalburgstrasse 157, Bad Homburg Tel: IR ITALY: Via Liguria 49, Borgaro, Torino Tel: IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: Data and specifications subject to change without notice. 8/97