IRLI620G PD HEXFET Power MOSFET V DSS = 200V. R DS(on) = 0.80Ω I D = 4.0A

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1 HEXFET Power MOSFET PD IRLI620G Isolated Package High Voltage Isolation = 2.5KVRMS Sink to Lead Creepage Dist. 4.8mm Logic-Level Gate Drive R DS(ON) Specified at V GS = 4V & 5V Fast Switching Ease of paralleling V DSS = 200V R DS(on) = 0.80Ω I D = 4.0 Description Third Generation HEXFETs from International Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low onresistance and cost-effectiveness. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 00 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 5.0V 4.0 I T C = 00 C Continuous Drain Current, V 5.0V 2.6 I DM Pulsed Drain Current 6 P C = 25 C Power Dissipation 30 W Linear Derating Factor 0.24 W/ C V GS Gate-to-Source Voltage ±0 V E S Single Pulse valanche Energy 62 mj I R valanche Current 4.0 E R Repetitive valanche Energy 3.0 mj dv/dt Peak Diode Recovery dv/dt 5.0 V/ns T J Operating Junction and -55 to + 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case) Mounting torque, 6-32 or M3 screw. 0 lbf in (.N m) Thermal Resistance Parameter Min. Typ. Max. Units R θjc Junction-to-Case 4. C/W R θj Junction-to-mbient 65 Revision 0

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 200 V V GS = 0V, ID = 250µ V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.27 V/ C Reference to 25 C, I D = m R DS(ON) Static Drain-to-Source On-Resistance 0.80 V GS = 5.0V, I D = 2.4 Ω.0 V GS = 4.0V, I D = 2.0 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ g fs Forward Transconductance.2 S V DS = 50V, I D = 3. I DSS Drain-to-Source Leakage Current 25 V DS = 200V, V GS = 0V µ 250 V DS = 60V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 00 V GS = 0V n Gate-to-Source Reverse Leakage -00 V GS = -0V Q g Total Gate Charge 6 I D = 5.2 Q gs Gate-to-Source Charge 2.7 nc V DS = 60V Q gd Gate-to-Drain ("Miller") Charge 9.6 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 4.2 V DD = 00V ns t r Rise Time 3 I D = 5.2 t d(off) Turn-Off Delay Time 8 R G = 9.0Ω t f Fall Time 7 R D = 20Ω, See Fig. 0 Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 360 V GS = 0V C oss Output Capacitance 9 pf V DS = 25V C rss Reverse Transfer Capacitance 27 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 4.0 (Body Diode) showing the I SM Pulsed Source Current integral reverse 6 (Body Diode) p-n junction diode. V SD Diode Forward Voltage.8 V T J = 25 C, I S = 4.0, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 5.2 Q rr Reverse RecoveryCharge..7 µc di/dt = 00/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) I SD 5.2, di/dt 95/µs, V DD V (BR)DSS, T J 50 C t=60s, ƒ=60hz V DD = 25V, starting T J = 25 C, L = 5.8mH R G = 25Ω, I S = 4.0. (See Figure 2) Pulse width 300µs; duty cycle 2%.

3 I D, Drain-to-Source Current () VGS TOP 7.50V 5.00V 4.00V 3.50V 3.00V 2.75V 2.50V BOTTOM 2.25V 2.25V I D, Drain-to-Source Current () 00 0 VGS TOP 7.50V 5.00V 4.00V 3.50V 3.00V 2.75V 2.50V BOTTOM 2.25V 2.25V 20µs PULSE WIDTH 20µs PULSE WIDTH 0.0 T C = 50 C 0. T C = 50 C V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics, T C = 25 o C Fig 2. Typical Output Characteristics, T C = 50 o C I D, Drain-to-Source Current () T J = 50 C T J = 25 C V DS = 50V 20µs PULSE WIDTH V 0.0 GS = 5.0V V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) I = 5.2 D T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 C, Capacitance (pf) V GS = 0V, f = MHz C iss = C gs + C gd, C ds SHORTED C rss = Cgd C oss = C ds + Cgd C iss C oss C rss V GS, Gate-to-Source Voltage (V) I D = 5.2 V DS = 60V V DS = 00V V DS = 40V V DS, Drain-to-Source Voltage (V) 0 FOR TEST CIRCUIT SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () 00 0 T J = 50 C T J = 25 C I D, Drain Current () 00 0 OPERTION IN THIS RE LIMITED BY RDS(on) 00µs ms 0ms T C = 25 C 00ms T J = 50 C V GS = 0V Single Pulse V SD, Source-to-Drain Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea

5 V DS R D 4.0 R G V GS D.U.T. V DD I D, Drain Current (mps) V Pulse Width µs Duty Factor 0. % Fig 0a. Switching Time Test Circuit T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0b. Switching Time Waveforms 0 Thermal Response (Z ) thjc 0. D = S IN G L E P UL S E (T H E R M L R E S P O N S E ) 2. P ea k T J = P D M x Z th JC + T C t, Rectangular Pulse Duration (sec) N o tes :. D u ty fa c tor D = t / t 2 PD M t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 5.0V Fig 2a. Unclamped Inductive Test Circuit Fig 2b. Unclamped Inductive Waveforms E S, Single Pulse valanche Energy (mj) ID TOP BOTTOM 4.0 V DD = 50V Starting T J, Juntion Temperature ( C) Fig 2c. Maximum valanche Energy Vs. Drain Current 5.0V Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD * * VGS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS

8 Package Outline TO-220 Full-Pak Part Marking Information TO-220 Full-Pak WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (30) EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: (44) IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 3L, Tel: (905) IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: IR ITLY: Via Liguria 49, 007 Borgaro, Torino Tel: (39) 45 0 IR FR EST: K&H Bldg., 2F, Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo 7 Tel: (03) IR SOUTHEST SI: 35 Outram Road, #0-02 Tan Boon Liat Building, 036 Tel: Data and specifications subject to change without notice.