IRFDC20. HEXFET Power MOSFET PD V DSS = 600V. R DS(on) = 4.4Ω I D = 0.32A

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1 HEXFET Power MOSFET Dynamic dv/dt Rating Repetitive Avalanche Rated For Automatic Insertion End Stackable Fast Switching Ease of paralleling Simple Drive Requirements PD IRFDC20 V DSS = 600V R DS(on) = 4.4Ω I D = 0.32A Description Third Generation HEXFETs from International Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low onresistance and cost-effectiveness. The 4-pin DIP package is a low-cost machine-insertable case style which can be stacked in multiple combinations on standard 0.1 inch pin centers. The dual drain serves as a thermal link to the mounting surface for power dissipation levels up to 1 watt. HD-1 Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10 V 0.32 I T C = 100 C Continuous Drain Current, V 10 V 0.20 A I DM Pulsed Drain Current 2.6 P C = 25 C Power Dissipation 1.0 W Linear Derating Factor W/ C V GS Gate-to-Source Voltage ±20 V E AS Single Pulse Avalanche Energy 50 mj I AR Avalanche Current 0.32 A E AR Repetitive Avalanche Energy 0.10 mj dv/dt Peak Diode Recovery dv/dt 3.0 V/ns T J Operating Junction and -55 to T STG Storage Temperature Range C Soldering Temperature, for 10 seconds 300 (1.6mm from case) Thermal Resistance Parameter Min. Typ. Max. Units R θja Junction-to-Ambient 120 C/W Revision 0

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 600 V V GS = 0V, ID = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.88 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 4.4 Ω V GS = 10.0V, I D = 0.19A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA g fs Forward Transconductance 1.4 S V DS = 50V, I D = 1.3A I DSS Drain-to-Source Leakage Current 25 V DS = 600V, V GS = 0V µa 250 V DS = 480V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 100 V GS = 20V na Gate-to-Source Reverse Leakage -100 V GS = -20V Q g Total Gate Charge 18 I D = 2.0A Q gs Gate-to-Source Charge 3.0 nc V DS = 360V Q gd Gate-to-Drain ("Miller") Charge 8.9 V GS = 10V t d(on) Turn-On Delay Time 10 V DD = 300V t r Rise Time 23 I D = 2.0A ns t d(off) Turn-Off Delay Time 30 R G = 18Ω t f Fall Time 25 R D = 150Ω L D Internal Drain Inductance 4.0 Between lead, 6mm (0.25in.) L S Internal Source Inductance 6.0 nh from package and center of die contact C iss Input Capacitance 350 V GS = 0V C oss Output Capacitance 48 pf V DS = 25V C rss Reverse Transfer Capacitance 8.6 ƒ = 1.0MHz Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 0.32 (Body Diode) showing the A I SM Pulsed Source Current integral reverse 2.6 (Body Diode) p-n junction diode. V SD Diode Forward Voltage 1.6 V T J = 25 C, I S = 0.32A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 2.0A Q rr Reverse RecoveryCharge µc di/dt = 100A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. I SD 4.4A, di/dt 90A/µs, V DD V (BR)DSS, T J 150 C V DD = 50V, starting T J = 25 C, L = 54mH R G = 25Ω, I AS = 1.3A. Pulse width 300µs; duty cycle 2%.

3 Fig 1. Typical Output Characteristics, T C = 25 o C Fig 2. Typical Output Characteristics, T C = 150 o C RDS(on), Drain-to-Source On Resistance (Normalized) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage ISD, Reverse Drain Current (Amps) Capacitance (pf) VGS, Gate-to-Source Voltage (volts) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

5 Fig 10a. Switching Time Test Circuit Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10b. Switching Time Waveforms Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 Fig 12a. Unclamped Inductive Test Circuit Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

7 dv/dt Test Circuit Peak Diode Recovery Test Circuit

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