PRELIMINARY. C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 Surface Mount (IRFBC20S) Low-profie through-hoe (IRFBC20L) Avaiabe in Tape & Ree (IRFBC20S) Dynamic dv/dt Rating 150 C Operating Temperature Fast Switching Fuy Avaanche Rated PRELIMINARY G PD HEXFET Power MOSFET D S V DSS = 600V R DS(on) = 4.4Ω I D = 2.2A Description Third generation HEXFETs from internationa Rectifier provide the designer with the best combination of fast switching, ruggedized device design, ow on-resistance and cost-effectiveness. The D 2 Pak is a surface mount power package capabe of the accommodatingdie sizes up to HEX-4. It provides the highest power capabiity and the owest possibe onresistance in any existing surface mount package. The D 2 Pak is suitabe for high current appications because of its ow interna connection resistance and can dissipate up to 2.0W in a typica surface mount appication. The through-hoe version (IRFBC20L) is avaiabe for ow-profie appications. 2 D Pak TO-262 Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10V 2.2 I T C = 100 C Continuous Drain Current, V 10V 1.4 A I DM Pused Drain Current 8.0 P A = 25 C Power Dissipation 3.1 W P C = 25 C Power Dissipation 50 W Linear Derating Factor 0.40 W/ C V GS Gate-to-Source Votage ± 20 V E AS Singe Puse Avaanche Energy 84 mj I AR Avaanche Current 2.2 A E AR Repetitive Avaanche Energy 5.0 mj dv/dt Peak Diode Recovery dv/dt ƒ 3.0 V/ns T J Operating Junction and -55 to T STG Storage Temperature Range C Sodering Temperature, for 10 seconds 300 (1.6mm from case ) Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 2.5 C/W R θja Junction-to-Ambient ( PCB Mounted,steady-state)** 40 7/22/97

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 600 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Votage Temp. Coefficient 0.88 V/ C Reference to 25 C, I D =1mA R DS(on) Static Drain-to-Source On-Resistance 4.4 Ω V GS =10V, I D = 1.3A V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µA g fs Forward Transconductance 1.4 S V DS = 50V, I D = 1.3A I DSS Drain-to-Source Leakage Current 100 V DS = 600V, V GS = 0V µa 500 V DS = 480V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 100 V GS = 20V na Gate-to-Source Reverse Leakage -100 V GS = -20V Q g Tota Gate Charge 18 I D = 2.0A Q gs Gate-to-Source Charge 3.0 nc V DS = 360V Q gd Gate-to-Drain ("Mier") Charge 8.9 V GS = 10V, See Fig. 6 and 13 t d(on) Turn-On Deay Time 10 V DD = 300V t r Rise Time 23 I D = 2.0A ns t d(off) Turn-Off Deay Time 30 R G = 18Ω t f Fa Time 25 R D = 150Ω, See Fig. 10 L S Interna Source Inductance 7.5 nh Between ead, and center of die contact C iss Input Capacitance 350 V GS = 0V C oss Output Capacitance 48 pf V DS = 25V C rss Reverse Transfer Capacitance 8.6 ƒ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo (Body Diode) 2.2 showing the A I SM Pused Source Current integra reverse G 8.0 (Body Diode) p-n junction diode. S V SD Diode Forward Votage 1.6 V T J = 25 C, I S = 2.2A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 2.0A Q rr Reverse Recovery Charge µc di/dt = 100A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S +L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. 11 ) V DD =50V, starting T J = 25 C, L =31mH R G = 25Ω, I AS = 2.2A. (See Figure 12) ƒ I SD 2.2A, di/dt 40A/µs, V DD V (BR)DSS, T J 150 C Puse width 300µs; duty cyce 2%. Uses IRFBC20 data and test conditions ** When mounted on 1" square PCB (FR-4 or G-10 Materia ). For recommended footprint and sodering techniques refer to appication note #AN-994.

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7 Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test + - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Appied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 14. For N-Channe HEXFETS

8 D 2 Pak Package Outine 1.40 (.055) MAX (.415) (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) RE F (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) RE F (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - G ATE 2 - DRA IN 3 - S OU RC E 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.100) 2X Part Marking Information D 2 Pak IN TER NATION AL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B 1M A PART NUMBER DATE CODE (YYWW ) YY = YEAR WW = WEEK

9 Package Outine TO-262 Outine Part Marking Information TO-262

10 Tape & Ree Information D 2 Pak TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) M AX (2.362) MIN. NOTES : 1. CO MFOR MS TO EIA CO NTRO LLING DIMENSION: MILLIMETER. 3. DIMENSIO N HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MA X. 4 WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, Te: (310) EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Te: IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Te: (905) IR GERMANY: Saaburgstrasse 157, Bad Homburg Te: IR ITALY: Via Liguria 49, Borgaro, Torino Te: IR FAR EAST: K&H Bdg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Te: IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Buiding, Singapore 0316 Te: Data and specifications subject to change without notice. 7/97