IRF540NSPbF IRF540NLPbF

Transcription

1 Advanced Process Technoogy Utra Low On-Resistance Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Fuy Avaanche Rated Lead-Free Description Advanced HEXFET Power MOSFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The D 2 Pak is a surface mount power package capabe of accommodating die sizes up to HEX-4. It provides the highest power capabiity and the owest possibe onresistance in any existing surface mount package. The D 2 Pak is suitabe for high current appications because of its ow interna connection resistance and can dissipate up to 2.0W in a typica surface mount appication. The through-hoe version (IRF540NL) is avaiabe for owprofie appications. Absoute Maximum Ratings G IRF540NSPbF IRF540NLPbF HEXFET Power MOSFET D S D 2 Pak IRF540NSPbF PD V DSS = 0V R DS(on) = 44mΩ I D = 33A TO-262 IRF540NLPbF Parameter Max. Units I T C = 25 C Continuous Drain V 33 I T C = 0 C Continuous Drain V 23 A I DM Pused Drain Current 1 P C = 25 C Power Dissipation 130 W Linear Derating Factor 0.87 W/ C Gate-to-Source Votage ± 20 V I AR Avaanche Current 16 A E AR Repetitive Avaanche Energy 13 mj dv/dt Peak Diode Recovery dv/dt ƒ 7.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Sodering Temperature, for seconds 300 (1.6mm from case ) Mounting torque, 6-32 or M3 srew bf in (1.1N m) Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.15 C/W R θja Junction-to-Ambient (PCB mount)** /18/04

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 0 V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Votage Temp. Coefficient 0.12 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 44 mω = V, I D = 16A (th) Gate Threshod Votage V V DS =, I D = 250µA g fs Forward Transconductance 21 S V DS = 50V, I D = 16A I DSS Drain-to-Source Leakage Current 25 V µa DS = 0V, = 0V 250 V DS = 80V, = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 = 20V na Gate-to-Source Reverse Leakage -0 = -20V Q g Tota Gate Charge 71 I D = 16A Q gs Gate-to-Source Charge 14 nc V DS = 80V Q gd Gate-to-Drain ("Mier") Charge 21 = V, See Fig. 6 and 13 t d(on) Turn-On Deay Time 11 V DD = 50V t r Rise Time 35 I D = 16A ns t d(off) Turn-Off Deay Time 39 R G = 5.1Ω t f Fa Time 35 = V, See Fig. Between ead, D L D Interna Drain Inductance 4 5 6mm (0.25in.) nh G from package L S Interna Source Inductance 7 5 and center of die contact S C iss Input Capacitance 1960 = 0V C oss Output Capacitance 250 V DS = 25V C rss Reverse Transfer Capacitance 40 pf ƒ = 1.0MHz, See Fig. 5 E AS Singe Puse Avaanche Energy mj I AS = 16A, L = 1.5mH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 33 (Body Diode) showing the A G I SM Pused Source Current integra reverse 1 (Body Diode) p-n junction diode. S V SD Diode Forward Votage 1.2 V T J = 25 C, I S = 16A, = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 16A Q rr Reverse Recovery Charge nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. 11) Starting T J = 25 C, L =1.5mH R G = 25Ω, I AS = 16A. (See Figure 12) ƒ I SD 16A, di/dt 340A/µs, V DD V (BR)DSS, T J 175 C Puse width 400µs; duty cyce 2%. This is a typica vaue at device destruction and represents operation outside rated imits. This is a cacuated vaue imited to T J = 175 C. Uses IRF540N data and test conditions. **When mounted on 1" square PCB (FR-4 or G- Materia). For recommended footprint and sodering techniques refer to appication note #AN

3 I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 1 T J = 25 C V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH 1 T J = 175 C V DS, Drain-to-Source Votage (V) Fig 1. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 25 C T J = 175 C V DS= 50V 20µs PULSE WIDTH , Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.5 I D = 33A = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current (A) IRF540NS/LPbF C, Capacitance (pf) 3000 VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds SHORTED C = 2500 rss Cgd Coss = Cds Cgd C 2000 iss C oss 500 C rss V DS, Drain-to-Source Votage (V), Gate-to-Source Votage (V) I = D 16A V DS = 80V V DS = 50V V DS = 20V FOR TEST CIRCUIT SEE FIGURE Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current (A) T J = 175 C T J = 25 C = 0 V V SD,Source-to-Drain Votage (V) T A = 25 C T J = 175 C Singe Puse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec 1msec msec V DS, Drain-toSource Votage (V) Fig 7. Typica Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Votage 4

5 I D, Drain Current (A) T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G V DS Puse Width 1 µs Duty Factor 0.1 % R D D U T Fig a Switching Time Test Circuit % t d(on) t r t d(off) t f Fig b Switching Time Waveforms - V DD Therma Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t Peak T J= P DM x Z thjc TC t 1, Rectanguar Puse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Therma Impedance, Junction-to-Case 5

6 15V V DS L DRIVER R G D.U.T IAS - V DD A 20V tp 0.01Ω Fig 12a Uncamped Inductive Test Circuit V (BR)DSS tp E AS, Singe Puse Avaanche Energy (mj) I D TOP 6.5A 11.3A BOTTOM 16A Starting T, Junction Temperature ( J C) Fig 12c Maximum Avaanche Energy Vs Drain Current I AS Fig 12b Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 13a Basic Gate Charge Waveform I G I D Current Samping Resistors Fig 13b Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D U T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G I SD controed by Duty Factor "D" D U T - Device Under Test - V DD * Reverse Poarity of D U T for P-Channe Driver Gate Drive Period P.W. D = P.W. Period [ =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Appied Votage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Rippe 5% Forward Drop [ V DD ] [ ] I SD *** = 5 0V for Logic Leve and 3V Drive Devices Fig 14 For N-channe HEXFET power MOSFETs 7

8 D 2 Pak Package Outine Dimensions are shown in miimeters (inches) D 2 Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 530S WIT H LOT CODE 8024 AS S E MB LE D ON WW 02, 2000 IN THE ASSEMBLY LINE "L" N ote: "P " in as s emby ine pos ition indicates "L ead-f ree" OR INT E R NAT IONAL R E CT IF IE R LOGO ASSEMBLY LOT CODE F530S PART NUMBER DAT E CODE YE AR 0 = 2000 WEEK 02 LINE L IN T E R N AT ION AL RECTIFIER LOGO AS S E MB L Y LOT CODE F 530S PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE 8

9 TO-262 Package Outine IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assemby ine position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE 9

10 D 2 Pak Tape & Ree Infomation Dimensions are shown in miimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065).90 (.429).70 (.421) (.457) (.449) 16. (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) MIN. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MAX. 4 Data and specifications subject to change without notice. This product has been designed and quaified for the industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.03/04

11 Note: For the most current drawings pease refer to the IR website at: