IRF530N. HEXFET Power MOSFET V DSS = 100V. R DS(on) = 90mΩ I D = 17A

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1 Advanced Process Technoogy Utra Low OnResistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fuy Avaanche Rated Description Advanced HEXFET Power MOSFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow onresistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The TO220 package is universay preferred for a commerciaindustria appications at power dissipation eves to approximatey 50 watts. The ow therma resistance and ow package cost of the TO220 contribute to its wide acceptance throughout the industry. G IRF530N HEXFET Power MOSFET D S TO220AB PD 935 V DSS = 0V R DS(on) = 90mΩ I D = 7A Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain V 7 I T C = 0 C Continuous Drain V 2 A I DM Pused Drain Current 60 P C = 25 C Power Dissipation 70 W Linear Derating Factor 0.47 W/ C GatetoSource Votage ± 20 V I AR Avaanche Current 9.0 A E AR Repetitive Avaanche Energy 7.0 mj dv/dt Peak Diode Recovery dv/dt ƒ 7.4 V/ns T J Operating Junction and 55 to 75 T STG Therma Resistance Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 632 or M3 srew bf in (.N m) Parameter Typ. Max. Units R θjc JunctiontoCase 2.5 R θcs CasetoSink, Fat, Greased Surface 0.50 C/W R θja JunctiontoAmbient 62 C 3/6/0

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Votage 0 V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Votage Temp. Coefficient 0. V/ C Reference to 25 C, I D = ma R DS(on) Static DraintoSource OnResistance 90 mω = V, I D = 9.0A (th) Gate Threshod Votage V V DS =, I D = 250µA g fs Forward Transconductance 2 S V DS = 50V, I D = 9.0A I DSS DraintoSource Leakage Current 25 V µa DS = 0V, = 0V 250 V DS = 80V, = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 0 = 20V na GatetoSource Reverse Leakage 0 = 20V Q g Tota Gate Charge 37 I D = 9.0A Q gs GatetoSource Charge 7.2 nc V DS = 80V Q gd GatetoDrain ("Mier") Charge = V, See Fig. 6 and 3 t d(on) TurnOn Deay Time 9.2 V DD = 50V t r Rise Time 22 I D = 9.0A ns t d(off) TurnOff Deay Time 35 R G = 2Ω t f Fa Time 25 = V, See Fig. Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 920 = 0V C oss Output Capacitance 30 V DS = 25V C rss Reverse Transfer Capacitance 9 pf ƒ =.0MHz, See Fig. 5 E AS Singe Puse Avaanche Energy mj I AS = 9.0A, L = 2.3mH SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 7 (Body Diode) showing the A G I SM Pused Source Current integra reverse 60 (Body Diode) pn junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 9.0A, = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 9.0A Q rr Reverse Recovery Charge nc di/dt = 0A/µs t on Forward TurnOn Time Intrinsic turnon time is negigibe (turnon is dominated by L S L D ) D S Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. ) Starting T J = 25 C, L = 2.3mH R G = 25Ω, I AS = 9.0A, =V (See Figure 2) ƒ I SD 9.0A, di/dt 4A/µs, V DD V (BR)DSS, T J 75 C Puse width 400µs; duty cyce 2%. This is a typica vaue at device destruction and represents operation outside rated imits. This is a cacuated vaue imited to T J = 75 C. 2

3 I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, DraintoSource Votage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, DraintoSource Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, DraintoSource Current (A) 0 T J = 25 C T J = 75 C V DS= 50V 20µs PULSE WIDTH , GatetoSource Votage (V) R DS(on), DraintoSource On Resistance (Normaized) 3.5 I D = 5A = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized OnResistance Vs. Temperature 3

4 I D, DraintoSource Current (A) IRF530N C, Capacitance (pf) 600 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED Crss = Cgd Coss = Cds Cgd 200 C iss 800 C oss 400 C rss 0 0 V DS, DraintoSource Votage (V), GatetoSource Votage (V) I = D 9.0A V DS = 80V V DS = 50V V DS = 20V FOR TEST CIRCUIT SEE FIGURE Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. DraintoSource Votage Fig 6. Typica Gate Charge Vs. GatetoSource Votage I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C = 0 V V SD,SourcetoDrain Votage (V) Tc = 25 C Tj = 75 C Singe Puse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec msec msec 0 00 V DS, DraintoSource Votage (V) Fig 7. Typica SourceDrain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 20 V DS R D I D, Drain Current (A) T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G Puse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit % t d(on) t r t d(off) t f Fig b. Switching Time Waveforms V DD Therma Response (Z thjc ) 0. D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, JunctiontoCase 5

6 R G V DS 20V tp L D.U.T IAS 0.0Ω Fig 2a. Uncamped Inductive Test Circuit tp 5V DRIVER V DD A V (BR)DSS E AS, Singe Puse Avaanche Energy (mj) TOP BOTTOM I D 3.7A 6.4A 9.0A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF Q GS Q GD D.U.T. V DS V G 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Samping Resistors Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer R G dv/dt controed by R G I SD controed by Duty Factor "D" D.U.T. Device Under Test V DD * Reverse Poarity of D.U.T for PChanne Driver Gate Drive Period P.W. D = P.W. Period [ =V ] *** D.U.T. I SD Waveform Reverse Recovery Current ReAppied Votage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Rippe 5% Forward Drop [ V DD ] [ ] I SD *** = 5.0V for Logic Leve and 3V Drive Devices Fig 4. For Nchanne HEXFET power MOSFETs 7

8 Package Outine TO220AB Dimensions are shown in miimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) A 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) (.255) 6. (.240) (.045) M IN LEAD ASSIGNMENTS GATE 2 DRAIN 3 SOU RC E 4 DRAIN 4.09 (.555) 3.47 (.530) 4.06 (.60) 3.55 (.40) 3X.40 (.055).5 (.045) 2.54 (.0) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) D IM E N S IO N IN G & TO L E R A N C ING P E R A N S I Y 4.5M, O U T LIN E C O N F O R M S TO JE D E C O U T LIN E TO 2 20 A B. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. Part Marking Information TO220AB EXAMPLE : THIS IS AN IRF W ITH ASSEMBLY LOT CODE 9BM INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CO DE IRF B M PART NUMBER DATE CODE (YYWW) YY = YEAR WW = WEEK A Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.3/0 8

9 Note: For the most current drawings pease refer to the IR website at: