Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 PD IRFPS38PbF HEXFET Power MOSFET Advanced Process Technoogy Utra Low On-Resistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fuy Avaanche Rated Lead-Free G D S V DSS = 0V R DS(on) = 0.009Ω I D = 70A Description The HEXFET Power MOSFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. Super-247 Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 70 I T C = 0 C Continuous Drain Current, V V 20 A I DM Pused Drain Current 670 P C = 25 C Power Dissipation 580 W Linear Derating Factor 3.8 W/ C V GS Gate-to-Source Votage ± 30 V E AS Singe Puse Avaanche Energy 350 mj I AR Avaanche Current 0 A E AR Repetitive Avaanche Energy 58 mj dv/dt Peak Diode Recovery dv/dt ƒ 2.3 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) C Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.26 R θcs Case-to-Sink, Fat, Greased Surface 0.24 C/W R θja Junction-to-Ambient //04

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 0 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Votage Temp. Coefficient 0. V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance Ω V GS = V, I D = 0A V GS(th) Gate Threshod Votage V V DS = V, I D = 250µA g fs Forward Transconductance 52 S V DS = 50V, I D = 0A I DSS Drain-to-Source Leakage Current 25 V µa DS = 0V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 30V na Gate-to-Source Reverse Leakage -0 V GS = -30V Q g Tota Gate Charge I D = 0A Q gs Gate-to-Source Charge nc V DS = 80V Q gd Gate-to-Drain ("Mier") Charge V GS = V t d(on) Turn-On Deay Time 24 V DD = 50V t r Rise Time 270 I D = 0A ns t d(off) Turn-Off Deay Time 45 R G =.03Ω t f Fa Time 40 V GS = V Between ead, D L D Interna Drain Inductance 5.0 6mm (0.25in.) nh G from package L S Interna Source Inductance 3 and center of die contact S C iss Input Capacitance 6790 V GS = 0V C oss Output Capacitance 2470 pf V DS = 25V C rss Reverse Transfer Capacitance 990 ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 740 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 80 V GS = 0V, V DS = 80V, ƒ =.0MHz C oss eff. Effective Output Capacitance 22 V GS = 0V, V DS = 0V to 80V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 70 (Body Diode) showing the A G I SM Pused Source Current integra reverse 670 (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 0A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 0A Q rr Reverse RecoveryCharge nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. ) Starting T J = 25 C, L = 0.27mH R G = 25Ω, I AS = 0A. (See Figure 2) ƒ I SD 0A, di/dt 350A/µs, V DD V (BR)DSS, T J 75 C Puse width 400µs; duty cyce 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss whie V DS is rising from 0 to 80% V DSS Cacuated continuous current based on maximum aowabe junction temperature. Package imitation current is 5A. 2

3 I D, Drain-to-Source Current (A) 0 0. VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 50µs PULSE WIDTH 0.0 T J = 25 C 0. 0 V DS, Drain-to-Source Votage (V) 50µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current (A) 0 T J = 75 C T J = 25 C V DS= 50V 50µs PULSE WIDTH V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.0 I D = 70A V GS = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current (A) C, Capacitance(pF) IRFPS38PbF V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) I = D 0A V DS = 80V V DS = 50V V DS = 20V FOR TEST CIRCUIT SEE FIGURE Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Votage (V) 0 0 Tc = 25 C Tj = 75 C Singe Puse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec msec msec 0 V DS, Drain-toSource Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 200 LIMITED BY PACKAGE V DS R D 60 R G V GS D.U.T. I D, Drain Current (A) V GS Puse Width µs Duty Factor 0. % Fig a. Switching Time Test Circuit - V DD 40 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t Peak T J = P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case 5

6 5V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS tp E AS, Singe Puse Avaanche Energy (mj) I D TOP 4A 7A BOTTOM 0A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. Q G 50KΩ Q GS Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3mA Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Appied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFET Power MOSFETs 7

8 Case Outine and Dimensions Super-247 Super-247 (TO-274AA) Part Marking Information EXAMPLE: THIS IS AN IRFPS37N50A WITH ASSEMBLY LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LO GO IRFPS37N50A 7 79C 89 PART NUMBER ASSEMBLY LOT CODE Note: "P" in assemby ine position indicates "Lead-Free" TOP DATE CODE (YYW W ) YY = YEAR WW = WEEK Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.09/04 8