IRFR3504ZPbF IRFU3504ZPbF

Transcription

1 Features Advanced Process Technoogy Utra Low On-Resistance 75 C Operating Temperature Fast Switching Repetitive Avaanche Aowed up to Tjmax Lead-Free Description This HEXFET Power MOSFET utiizes the atest processing techniques to achieve extremey ow on-resistance per siicon area. Additiona features of this design are a 75 C junction operating temperature, fast switching speed and improved repetitive avaanche rating. These features combine to make this design an extremey efficient and reiabe device for use in a wide variety of appications. Absoute Maximum Ratings Parameter I T C = 25 C Continuous Drain Current, V V (Siicon Limited) IRFR354ZPbF IRFU354ZPbF HEXFET Power MOSFET V DSS = 4V R DS(on) = 9.mΩ I D = 42A HEXFET is a registered trademark of Internationa Rectifier. G D S D-Pak IRFR354ZPbF I-Pak IRFU354ZPbF Units I T C = C Continuous Drain Current, V V 54 A I T C = 25 C Continuous Drain Current, V V (Package Limited) 42 I DM Pused Drain Current c 3 P C = 25 C Power Dissipation 9 W Linear Derating Factor.6 W/ C V GS Gate-to-Source Votage ± 2 V E AS (Thermay imited) Singe Puse Avaanche Energyd 77 mj E AS (Tested ) Singe Puse Avaanche Energy Tested Vaue h I AR Avaanche Currentc See Fig.2a, 2b, 5, 6 A E AR Repetitive Avaanche Energy g mj T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Sodering Temperature, for seconds 3 (.6mm from case ) bfyin (.Nym) Mounting Torque, 6-32 or M3 screw Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.66 R θja Junction-to-Ambient (PCB mount) i 4 C/W R θja Junction-to-Ambient Max. 77 PD B 9/27/

2 IRFR/U354ZPbF Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Votage 4 V Conditions V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Votage Temp. Coefficient.32 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance mω V GS = V, I D = 42A e V GS(th) Gate Threshod Votage V V DS = V GS, I D = 25µA gfs Forward Transconductance 32 S V DS = V, I D = 42A I DSS Drain-to-Source Leakage Current 2 µa V DS = 4V, V GS = V 25 V DS = 4V, V GS = V, T J = 25 C I GSS Gate-to-Source Forward Leakage 2 na V GS = 2V Gate-to-Source Reverse Leakage -2 V GS = -2V Q g Tota Gate Charge 3 45 I D = 42A Q gs Gate-to-Source Charge 9.6 nc V DS = 32V Q gd Gate-to-Drain ("Mier") Charge 2 V GS = V e t d(on) Turn-On Deay Time 5 V DD = 2V t r Rise Time 74 I D = 42A t d(off) Turn-Off Deay Time 3 ns R G = 5 Ω t f Fa Time 38 V GS = V e L D Interna Drain Inductance 4.5 Between ead, D nh 6mm (.25in.) L S Interna Source Inductance 7.5 from package G and center of die contact S C iss Input Capacitance 5 V GS = V C oss Output Capacitance 34 V DS = 25V C rss Reverse Transfer Capacitance 9 pf ƒ =.MHz C oss Output Capacitance V GS = V, V DS =.V, ƒ =.MHz C oss Output Capacitance 34 V GS = V, V DS = 32V, ƒ =.MHz C oss eff. Effective Output Capacitance 46 V GS = V, V DS = V to 32V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 42 MOSFET symbo (Body Diode) A showing the I SM Pused Source Current 3 integra reverse (Body Diode)Ãc p-n junction diode. V SD Diode Forward Votage.3 V T J = 25 C, I S = 42A, V GS = V e t rr Reverse Recovery Time 8 27 ns T J = 25 C, I F = 42A, V DD = 2V Q rr Reverse Recovery Charge nc di/dt = A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by LSLD) 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) Gfs, Forward Transconductance (S) I D, Drain-to-Source Current (A) IRFR/U354ZPbF VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V. 4.5V 3µs PULSE WIDTH Tj = 25 C. V DS, Drain-to-Source Votage (V) 4.5V 3µs PULSE WIDTH Tj = 75 C. V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics. 6 T J = 75 C 5. T J = 75 C 4 T J = 25 C. 3. T J = 25 C 2 V DS = 2V 3µs PULSE WIDTH V GS, Gate-to-Source Votage (V) V DS = V 38µs PULSE WIDTH I D, Drain-to-Source Current (A) Fig 3. Typica Transfer Characteristics Fig 4. Typica Forward Transconductance Vs. Drain Current 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Votage (V) IRFR/U354ZPbF V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss I D = 42A V DS = 32V VDS= 2V VDS= 8.V 8 5 Coss Crss V DS, Drain-to-Source Votage (V) 4 FOR TEST CIRCUIT SEE FIGURE Q G Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage. OPERATION IN THIS AREA LIMITED BY R DS (on). T J = 75 C. µsec T J = 25 C. V GS = V V SD, Source-toDrain Votage (V). Tc = 25 C Tj = 75 C Singe Puse msec msec V DS, Drain-toSource Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normaized) IRFR/U354ZPbF 8 LIMITED BY PACKAGE 2. I D = 42A V GS = V T C, Case Temperature ( C) T J, Junction Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig. Normaized On-Resistance Vs. Temperature D =.5 Therma Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ) R R 2 R R 2 τ J τ J τ τ τ 2 τ 2 Ci= τi/ri Ci i Ri E-6 E t, Rectanguar Puse Duration (sec) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case Ri ( C/W) τi (sec) τ C τ

6 V GS(th) Gate threshod Votage (V) E AS, Singe Puse Avaanche Energy (mj) IRFR/U354ZPbF V DS L 5V DRIVER I D TOP 5.A 6.4A BOTTOM 42A R G 2V V GS tp D.U.T IAS.Ω - V DD A Fig 2a. Uncamped Inductive Test Circuit tp V (BR)DSS Starting T J, Junction Temperature ( C) I AS Fig 2b. Uncamped Inductive Waveforms Fig 2c. Maximum Avaanche Energy Vs. Drain Current V Q G Q GS Q GD 4.5 V G 4. Charge Fig 3a. Basic Gate Charge Waveform I D = 25µA K DUT L VCC T J, Temperature ( C ) Fig 3b. Gate Charge Test Circuit Fig 4. Threshod Votage Vs. Temperature 6

7 Avaanche Current (A) E AR, Avaanche Energy (mj) IRFR/U354ZPbF Duty Cyce = Singe Puse..5. Aowed avaanche Current vs avaanche pusewidth, tav assuming Tj = 25 C due to avaanche osses. Note: In no case shoud Tj be aowed to exceed Tjmax..E-6.E-5.E-4.E-3.E-2.E- tav (sec) Fig 5. Typica Avaanche Current Vs.Pusewidth TOP Singe Puse BOTTOM % Duty Cyce I D = 42A Starting T J, Junction Temperature ( C) Notes on Repetitive Avaanche Curves, Figures 5, 6: (For further info, see AN-5 at Avaanche faiures assumption: Purey a therma phenomenon and faiure occurs at a temperature far in excess of T jmax. This is vaidated for every part type. 2. Safe operation in Avaanche is aowed as ong ast jmax is not exceeded. 3. Equation beow based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per singe avaanche puse. 5. BV = Rated breakdown votage (.3 factor accounts for votage increase during avaanche). 6. I av = Aowabe avaanche current. 7. T = Aowabe rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avaanche. D = Duty cyce in avaanche = t av f Z thjc (D, t av ) = Transient therma resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avaanche Energy I av = 2DT/ [.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av 7

8 IRFR/U354ZPbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controed by RG Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Appied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 7. Peak Diode Recovery dv/dt Test Circuit for N-Channe HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Puse Width µs Duty Factor. % Fig 8a. Switching Time Test Circuit V DS 9% % V GS t d(on) t r t d(off) t f Fig 8b. Switching Time Waveforms 8

9 IRFR/U354ZPbF D-Pak (TO-252AA) Package Outine Dimensions are shown in miimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR2 WITH ASSEMBLY LOT CODE 234 AS SEMBLED ON WW 6, 2 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates "Lead-Free" "P" in assemby ine position indicates "Lead-F ree" quaification to the cons umer-eve INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFR2 6A 2 34 PART NUMBER DATE CODE YEAR = 2 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFR PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) P = DESIGNATES LEAD-FREE PRODUCT QUALIFIED TO THE CONSUMER LEVEL (OPTIONAL) YEAR = 2 WEEK 6 A = ASSEMBLY SITE CODE Notes:. For an Automotive Quaified version of this part pease seehttp:// 2. For the most current drawing pease refer to IR website at 9

10 IRFR/U354ZPbF I-Pak (TO-25AA) Package Outine Dimensions are shown in miimeters (inches) I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU2 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 2 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFU2 9A PART NUMBER DATE CODE YEAR = 2 WEEK 9 LINE A OR INT ERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR = 2 WEEK 9 A = ASSEMBLY SITE CODE Notes:. For an Automotive Quaified version of this part pease seehttp:// 2. For the most current drawing pease refer to IR website at

11 IRFR/U354ZPbF D-Pak (TO-252AA) Tape & Ree Information Dimensions are shown in miimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA INCH NOTES :. OUTLINE CONFORMS TO EIA-48. Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. ). Limited by T Jmax, starting T J = 25 C, L =.9mH R G = 25Ω, I AS = 42A, V GS =V. Part not recommended for use above this vaue. ƒ Puse width.ms; duty cyce 2%. 6 mm C oss eff. is a fixed capacitance that gives the same charging time as C oss whie V DS is rising from to 8% V DSS. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typica repetitive avaanche performance. This vaue determined from sampe faiure popuation. % tested to this vaue in production. When mounted on " square PCB (FR-4 or G- Materia). For recommended footprint and sodering techniques refer to appication note #AN-994 Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 9245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.9/2