IRFZ48VS. HEXFET Power MOSFET V DSS = 60V. R DS(on) = 12mΩ I D = 72A

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1 Advanced Process Technoogy Utra Low OnResistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fuy Avaanche Rated Optimized for SMPS Appications Description Advanced HEXFET Power MOSFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow onresistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The D 2 Pak is a surface mount power package capabe of accommodating die sizes up to HEX4. It provides the highest power capabiity and the owest possibe onresistance in any existing surface mount package. The D 2 Pak is suitabe for high current appications because of its ow interna connection resistance and can dissipate up to 2.0W in a typica surface mount appication. G IRFZ48VS HEXFET Power MOSFET D S V DSS = 60V R DS(on) = 2mΩ I D = 72A D 2 Pak PD 9405A Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 72 I T C = 0 C Continuous Drain Current, V V 5 A I DM Pused Drain Current 290 P C = 25 C Power Dissipation 50 W Linear Derating Factor.0 W/ C V GS GatetoSource Votage ± 20 V E AS Singe Puse Avaanche Energy 66 mj I AR Avaanche Current 72 A E AR Repetitive Avaanche Energy 5 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.3 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range C Sodering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 632 or M3 srew bf in (.N m) Therma Resistance Parameter Typ. Max. Units R θjc JunctiontoCase.0 R θcs CasetoSink, Fat, Greased Surface 0.50 C/W R θja JunctiontoAmbient /8/0

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Votage 60 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Votage Temp. Coefficient V/ C Reference to 25 C, I D = ma R DS(on) Static DraintoSource OnResistance 2.0 mω V GS = V, I D = 43A V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µA g fs Forward Transconductance 35 S V DS = 25V, I D = 43A I DSS DraintoSource Leakage Current 25 V µa DS = 60V, V GS = 0V 250 V DS = 48V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 0 V GS = 20V na GatetoSource Reverse Leakage 0 V GS = 20V Q g Tota Gate Charge I D = 72A Q gs GatetoSource Charge 29 nc V DS = 48V Q gd GatetoDrain ("Mier") Charge 36 V GS = V, See Fig. 6 and 3 t d(on) TurnOn Deay Time 7.6 V DD = 30V t r Rise Time 200 I D = 72A ns t d(off) TurnOff Deay Time 57 R G = 9.Ω t f Fa Time 66 R D = 0.34Ω, See Fig. Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 985 V GS = 0V C oss Output Capacitance 496 V DS = 25V C rss Reverse Transfer Capacitance 9 pf ƒ =.0MHz, See Fig. 5 D S SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 72 (Body Diode) showing the A G I SM Pused Source Current integra reverse 290 (Body Diode) pn junction diode. S V SD Diode Forward Votage 2.0 V T J = 25 C, I S = 72A, V GS = 0V t rr Reverse Recovery Time 70 0 ns T J = 25 C, I F = 72A Q rr Reverse Recovery Charge nc di/dt = 0A/µs t on Forward TurnOn Time Intrinsic turnon time is negigibe (turnon is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 64µH R G = 25Ω, I AS = 72A. (See Figure 2) ƒ I SD 72A, di/dt 5A/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%. 2

3 I D, DraintoSource Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V I D, DraintoSource Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, DraintoSource Votage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, DraintoSource Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, DraintoSource Current (A) 00 0 T J = 25 C T J= 75 C V DS = 25V 20µs PULSE WIDTH V GS, GatetoSource Votage (V) R DS(on), DraintoSource On Resistance (Normaized) 3.0 I D = 72A V GS = V T J, Junction Temperature( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized OnResistance Vs. Temperature 3

4 C, Capacitance(pF) IRFZ48VS V GS = 0V, f = MHZ C is = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 V DS, DraintoSource Votage (V) V GS, GatetoSource Votage (V) I D = 72A V DS= 48V V DS= 30V V DS= 2V Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. DraintoSource Votage Fig 6. Typica Gate Charge Vs. GatetoSource Votage I SD, Reverse Drain Current (A) 00 0 T J= 75 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Votage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms ms TC = 25 C TJ = 75 C Singe Puse 0 00 V DS, DraintoSource Votage (V) Fig 7. Typica SourceDrain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 80 V DS R D I D, Drain Current (A) V GS D.U.T. R G V Puse Width µs Duty Factor 0. % Fig a. Switching Time Test Circuit V DS 90% V DD T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig 9. Maximum Drain Current Vs. Case Temperature Fig b. Switching Time Waveforms Therma Response(Z thjc ) 0. D = SINGLE PULSE t2 0.0 (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J= P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t Fig. Maximum Effective Transient Therma Impedance, JunctiontoCase 5

6 R G V DS 20V tp Fig 2a. Uncamped Inductive Test Circuit tp I AS L D.U.T 0.0Ω 5V V (BR)DSS DRIVER V DD A E AS, Singe Puse Avaanche Energy (mj) I D TOP 29A 5A BOTTOM 72A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF V Q GS Q GD D.U.T. V DS V GS V G 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Samping Resistors Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD ReAppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For NChanne HEXFETS 7

8 D 2 Pak Package Outine D 2 Pak Part Marking Infor THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.5/0 8

9 Note: For the most current drawings pease refer to the IR website at: