SMPS MOSFET. V DSS R DS(on) max I D. l TO-220AB

Transcription

1 PD SMPS MOSFET IRFB42N20D Appications High frequency DCDC converters Motor Contro Uninterrutibe Power Suppies HEXFET Power MOSFET V DSS R DS(on) max I D 200V 0.055Ω 44A Benefits Low GatetoDrain Charge to Reduce Switching Losses Fuy Characterized Capacitance Incuding Effective C OSS to Simpify Design, (See App. Note AN0) Fuy Characterized Avaanche Votage and Current TO220AB Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 44 I T C = 0 C Continuous Drain Current, V V 3 A I DM Pused Drain Current 80 P A = 25 C Power Dissipation 2.4 W P C = 25 C Power Dissipation 330 Linear Derating Factor 2.2 W/ C V GS GatetoSource Votage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 2.5 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range C Sodering Temperature, for seconds 300 (.6mm from case ) Mounting torqe, 632 or M3 screw bf in (.N m) Therma Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 0.45 R θcs CasetoSink, Fat, Greased Surface 0.50 C/W R θja JunctiontoAmbient 62 Notes through are on page 8 5/7/0

2 T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Votage 200 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Votage Temp. Coefficient 0.26 V/ C Reference to 25 C, I D = ma R DS(on) Static DraintoSource OnResistance Ω V GS = V, I D = 26A V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µA 25 V µa DS = 200V, V GS = 0V I DSS DraintoSource Leakage Current 250 V DS = 60V, V GS = 0V, T J = 50 C GatetoSource Forward Leakage 0 V GS = 30V I GSS na GatetoSource Reverse Leakage 0 V GS = 30V T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 2 S V DS = 50V, I D = 26A Q g Tota Gate Charge 9 40 I D = 26A Q gs GatetoSource Charge nc V DS = 60V Q gd GatetoDrain ("Mier") Charge V GS = V, t d(on) TurnOn Deay Time 8 V DD = 0V t r Rise Time 69 ns I D = 26A t d(off) TurnOff Deay Time 29 R G =.8Ω t f Fa Time 32 V GS = V C iss Input Capacitance 3430 V GS = 0V C oss Output Capacitance 530 V DS = 25V C rss Reverse Transfer Capacitance 0 pf ƒ =.0MHz C oss Output Capacitance 53 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 2 V GS = 0V, V DS = 60V, ƒ =.0MHz C oss eff. Effective Output Capacitance 400 V GS = 0V, V DS = 0V to 60V Avaanche Characteristics Parameter Typ. Max. Units E AS Singe Puse Avaanche Energy 5 mj I AR Avaanche Current 26 A E AR Repetitive Avaanche Energy 33 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 44 (Body Diode) showing the A G I SM Pused Source Current integra reverse 80 (Body Diode) pn junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 26A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 26A Q rr Reverse RecoveryCharge nc di/dt = 0A/µs t on Forward TurnOn Time Intrinsic turnon time is negigibe (turnon is dominated by L S L D ) 2

3 I D, DraintoSource Current (A) 0 0. VGS TOP 5V V 8.0V 7.0V 6.5V 6.0V 5.5V BOTTOM 5.0V 5.0V I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.5V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH T J = 25 C V DS, DraintoSource Votage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, DraintoSource Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, DraintoSource Current (A) 0 T J = 75 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, GatetoSource Votage (V) R DS(on), DraintoSource On Resistance (Normaized) 3.5 I D = 44A V GS = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized OnResistance Vs. Temperature 3

4 I D, DraintoSource Current (A) C, Capacitance(pF) IRFB42N20D Ciss Coss Crss V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 0 V DS, DraintoSource Votage (V) V GS, GatetoSource Votage (V) I D = 26A V DS = 60V V DS = 0V V DS = 40V FOR TEST CIRCUIT SEE FIGURE Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. DraintoSource Votage Fig 6. Typica Gate Charge Vs. GatetoSource Votage OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Votage (V) 0 0. Tc = 25 C Tj = 75 C Singe Puse 0µsec msec msec 0 V DS, DraintoSource Votage (V) Fig 7. Typica SourceDrain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 50 V DS R D I D, Drain Current (A) Fig a. Switching Time Test Circuit V DS 90% R G V GS V Puse Width µs Duty Factor 0. % D.U.T. V DD T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, JunctiontoCase 5

6 R G V DS 20V V GS tp Fig 2a. Uncamped Inductive Test Circuit tp L D.U.T IAS 0.0Ω V (BR)DSS 5V DRIVER V DD A E AS, Singe Puse Avaanche Energy (mj) TOP BOTTOM I D A 9A 26A Starting T, Junction Temperature ( J C) I AS Fig 2c. Maximum Avaanche Energy Vs. Drain Current Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. V Q GS Q G Q GD 2V.2µF 50KΩ.3µF D.U.T. V DS V G V GS 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Samping Resistors Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD ReAppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For NChanne HEXFET Power MOSFETs 7

8 TO220AB Package Outine Dimensions are shown in miimeters (inches) 2.87 (.3) 2.62 (.3) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530).54 (.45).29 (.405) (.255) 6. (.240) 3.78 (.49) 3.54 (.39) A.5 (.045) MIN 4.06 (.60) 3.55 (.40) 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) LEAD ASSIGNMENTS G ATE 2 DR AIN 3 SOURCE 4 DR AIN 3X.40 (.055).5 (.045) 2.54 (.0) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) DIMENSIONING & TOLERANCING PER ANSI Y4.5M, O UTLINE CO NF ORMS TO JEDEC OUTLINE TO220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO220AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO AS S E MB L Y LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C Notes: Repetitive rating; puse width imited by max. junction temperature. Starting T J = 25 C, L =.45mH R G = 25Ω, I AS = 26A, V GS =V ƒ I SD 26A, di/dt A/µs, V DD V (BR)DSS, T J 75 C Puse width 400µs; duty cyce 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss whie V DS is rising from 0 to 80% V DSS Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.5/0 8

9 Note: For the most current drawings pease refer to the IR website at: