IRL3803VSPbF IRL3803VLPbF HEXFET Power MOSFET

Transcription

1 l Logic-Level Gate Drive l Advanced Process Technology l Surface Mount (IRL3803VS) l Low-profile through-hole (IRL3803VL) l 175 C Operating Temperature l Fast Switching G l Fully Avalanche Rated l Lead-Free Description Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. IRL3803VSPbF IRL3803VLPbF HEXFET Power MOSFET D S PD V DSS = 30V R DS(on) = 5.5mΩ I D = 140A The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. D 2 Pak IRL3803VS TO-262 IRL3803VL Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain 10V ˆ 140 I T C = 100 C Continuous Drain 10V ˆ 110 A I DM Pulsed Drain Current ˆ 470 P A = 25 C Power Dissipation 3.8 W P C = 25 C Power Dissipation 200 W Linear Derating Factor 1.4 W/ C Gate-to-Source Voltage ± 16 V I AR Avalanche Current 71 A E AR Repetitive Avalanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒˆ 5.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 C/W R θja Junction-to-Ambient (PCB Mounted, steady state) /4/05

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 30 V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA ˆ R DS(on) Static Drain-to-Source On-Resistance 5.5 = 10V, I D = 71A mω 7.5 = 4.5V, I D = 59A (th) Gate Threshold Voltage 1.0 V V DS =, I D = 250µA ˆ g fs Forward Transconductance 82 S V DS = 25V, I D = 71A ˆ I DSS Drain-to-Source Leakage Current 25 V µa DS = 30V, = 0V 250 V DS = 24V, = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 100 = 16V na Gate-to-Source Reverse Leakage -100 = -16V Q g Total Gate Charge 76 I D = 71A Q gs Gate-to-Source Charge 19 nc V DS = 24V Q gd Gate-to-Drain ("Miller") Charge 35 = 4.5V, See Fig. 6 and 13 ˆ t d(on) Turn-On Delay Time 16 V DD = 15V t r Rise Time 180 I D = 71A t d(off) Turn-Off Delay Time 29 R G = 1.3Ω t f Fall Time 37 = 4.5V, See Fig. 10 ˆ Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 3720 = 0V C oss Output Capacitance 1480 V DS = 25V C rss Reverse Transfer Capacitance 270 pf ƒ = 1.0MHz, See Fig. 5 ˆ E AS Single Pulse Avalanche Energy ˆ mj I AS = 71A, L = 0.16mH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 140 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 470 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.2 V T J = 25 C, I S = 71A, = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 71A Q rr Reverse Recovery Charge nc di/dt = 100A/µs ˆ t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11) Starting T J = 25 C, L = 160µH R G = 25Ω, I AS = 71A, =10V (See Figure 12) ƒ I SD 71A, di/dt 110A/µs, V DD V (BR)DSS, T J 175 C Pulse width 400µs; duty cycle 2%. This is a typical value at device destruction and represents operation outside rated limits. This is a calculated value limited to T J = 175 C. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. ˆ Uses IRL3803 data and test conditions. This is applied to D 2 Pak, when mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN D S

3 I D, Drain-to-Source Current (A) 100 VGS TOP 15V 10V 4.5V 3.7V 3.5V 3.3V 3.0V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH 10 T J = 25 C V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 100 VGS TOP 15V 10V 4.5V 3.7V 3.5V 3.3V 3.0V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH T J = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 100 T J = 25 C T J = 175 C V DS= 15V 20µs PULSE WIDTH , Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 120A = 10V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current (A) IRL3803VS/IRL3803VLPbF C, Capacitance (pf) 6000 VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds SHORTED Crss = Cgd 5000 Coss = Cds Cgd 4000 C iss 3000 C oss 2000 C rss V DS, Drain-to-Source Voltage (V), Gate-to-Source Voltage (V) I = D 71A V DS = 24V V DS = 15V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) T J = 175 C T J = 25 C = 0 V V SD,Source-to-Drain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) 100µsec 1msec 10msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 160 LIMITED BY PACKAGE V DS R D I D, Drain Current (A) T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G Pulse Width 1 µs Duty Factor 0.1 % D.U.T. Fig 10a. Switching Time Test Circuit 10% t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms - V DD 1 Thermal Response (Z thjc ) 0.1 D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t Peak T J = P DM x Z thjc TC t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS 20V tp Fig 12a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.01Ω 15V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 29A 50A 71A Starting T, Junction Temperature ( J C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ =10V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET power MOSFETs 7

8 D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 530S WIT H LOT CODE 8024 AS S E MB LE D ON WW 02, 2000 IN THE ASSEMBLY LINE "L" N ote: "P " in as s embly line pos ition indicates "L ead-f ree" OR INT E R NAT IONAL R E CT IF IE R LOGO ASSEMBLY LOT CODE F530S PART NUMBER DAT E CODE YE AR 0 = 2000 WEEK 02 LINE L IN T E R N AT ION AL RECTIFIER LOGO AS S E MB L Y LOT CODE F 530S PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE 8

9 TO-262 Package Outline IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line pos ition indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE 9

10 D 2 Pak Tape & Reel Infomation Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) MIN. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information. 01/

11 Note: For the most current drawings please refer to the IR website at: