IRFPC60LC PD HEXFET Power MOSFET V DSS = 600V. R DS(on) = 0.40Ω I D = 16A

Transcription

1 HEXFET Power MOSFET Ultra Low Gate Charge Reduced Gate Drive Requirement Enhanced 30V V gs Rating Reduced C iss, C oss, C rss Isolated Central Mounting Hole Dynamic dv/dt Rated Repetitive Avalanche Rated Description PD IRFPC60LC V S = 600V R (on) = 0.40Ω I D = 6A This new series of Low Charge HEXFET Power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing advanced Hexfet technology the device improvements allow for reduced gate drive requirements, faster switching speeds and increased total system savings. These device improvements combined with the proven ruggedness and reliability of HEXFETs offer the designer a new standard in power transistors for switching applications. The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. The TO-247 is similar but superior to the earlier TO-28 package because of its isolated mounting hole. Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V 6 I T C = 00 C Continuous Drain Current, V 0V 0 A I DM Pulsed Drain Current 64 P C = 25 C Power Dissipation 280 W Linear Derating Factor 2.2 W/ C V GS Gate-to-Source Voltage ±30 V E AS Single Pulse Avalanche Energy 000 mj I AR Avalanche Current 6 A E AR Repetitive Avalanche Energy 28 mj dv/dt Peak Diode Recovery dv/dt 3.0 V/ns T J Operating Junction and -55 to + 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case) Mounting torque, 6-32 or M3 screw. 0 lbf in (.N m) Thermal Resistance Parameter Min. Typ. Max. Units R θjc Junction-to-Case 0.45 R θcs Case-to-Sink, Flat, Greased Surface 0.24 C/W R θja Junction-to-Ambient 40 Revision 0

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)S Drain-to-Source Breakdown Voltage 600 V V GS = 0V, ID = 250µA V (BR)S/ T J Breakdown Voltage Temp. Coefficient 0.63 V/ C Reference to 25 C, I D = ma R (ON) Static Drain-to-Source On-Resistance 0.40 Ω V GS = 0V, I D = 9.6A V GS(th) Gate Threshold Voltage V V = V GS, I D = 250µA g fs Forward Transconductance S V = 50V, I D = 9.6A 25 V = 600V, V GS = 0V I S Drain-to-Source Leakage Current µa 250 V = 480V, V GS = 0V, T J = 25 C Gate-to-Source Forward Leakage 00 V GS = 20V I GSS na Gate-to-Source Reverse Leakage -00 V GS = -20V Q g Total Gate Charge 20 I D = 6A Q gs Gate-to-Source Charge 29 nc V = 360V Q gd Gate-to-Drain ("Miller") Charge 48 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 7 V DD = 300V t r Rise Time 57 I D = 6A ns t d(off) Turn-Off Delay Time 43 R G = 4.3Ω t f Fall Time 38 R D = 8Ω, See Fig. 0 Between lead, L D Internal Drain Inductance 5.0 6mm (0.25in.) nh from package L S Internal Source Inductance 3 and center of die contact C iss Input Capacitance 3500 V GS = 0V C oss Output Capacitance 400 pf V = 25V C rss Reverse Transfer Capacitance 39 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 6 (Body Diode) showing the A I SM Pulsed Source Current integral reverse 64 (Body Diode) p-n junction diode. V SD Diode Forward Voltage.8 V T J = 25 C, I S = 6A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 6A Q rr Reverse Recovery Charge µc di/dt = 00A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) I SD 6A, di/dt 40A/µs, V DD V (BR)S, T J 50 C V DD = 25V, starting T J = 25 C, L = 7.2mH R G = 25Ω, I AS = 6A. (See Figure 2) Pulse width 300µs; duty cycle 2%.

3 I, Drain-to-Source Current (A) D VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I, Drain-to-Source Current (A) D VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T C = 25 C V, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 0.0 T C = 50 C V, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics, T C = 25 o C Fig 2. Typical Output Characteristics, T C = 50 o C I D, D rain-to-so urce Cu rre nt (A ) T J = 5 0 C T J = 2 5 C V D S = 0 0V 2 0 µs P U LS E W ID TH V G S, G a te-to-s o urce V olta ge (V ) R (on), Drain-to-Source On Resistance (Normalized) I D = 6A V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 C, Capacitance (pf) V GS = 0V, f = MHz C iss = C gs + C gd, C ds SHORTED C rss = Cgd C oss = C ds + C gd C iss 00 0 C oss C rss V, Drain-to-Source Voltage (V) V, Gate-to-Source Voltage (V) GS I D = 6A V = 360V V = 240V V = 20V FOR TEST CIRCUIT SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 50 C T J = 25 C V GS = 0V V SD, Source-to-Drain Voltage (V) I D, Drain Current (A) 000 OPERATION IN THIS AREA LIMITED BY R(on) 00 0µs 00µs 0 ms T C = 25 C T J = 50 C 0ms Single Pulse V, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

5 V R D 6 R G V GS D.U.T. V DD I D, Drain Current (Amps) V Pulse Width µs Duty Factor 0. % Fig 0a. Switching Time Test Circuit T, Case Temperature ( C) C Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0b. Switching Time Waveforms T herm al R esponse (Z thjc ) D = S IN G L E P UL SE (T H E R M AL R E S P O N S E ) N o tes :. D u ty fa c tor D = t / t 2 2. P e ak T J = P D M x Z th JC + T C t, R ectangular Pulse D uration (sec) PD M t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 0 V Fig 2a. Unclamped Inductive Test Circuit Fig 2b. Unclamped Inductive Waveforms E AS, Single Pulse Avalanche Energy (mj) ID TOP 7.2A 0A BOTTOM 6A V DD = 50V Starting T J, Juntion Temperature ( C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD * * VGS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS

8 Package Outline TO-247AC Part Marking Information TO-247AC EXAMPLE : THIS IS AN IRFPE30 WITH ASSEMBLY LOT CODE 3AQ INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFPE30 3AQ 9302 PART NUMBER DATE CODE (YYWW) YY = YEAR WW WEEK A WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (30) EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: (44) IR CANADA: 732 Victoria Park Ave., Suite 20, Markham, Ontario L3R 3L, Tel: (905) IR GERMANY: Saalburgstrasse 57, 6350 Bad Homburg Tel: IR ITALY: Via Liguria 49, 007 Borgaro, Torino Tel: (39) 45 0 IR FAR EAST: K&H Bldg., 2F, Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo 7 Tel: (03) IR SOUTHEAST ASIA: 35 Outram Road, #0-02 Tan Boon Liat Building, 036 Tel: Data and specifications subject to change without notice.