C Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Transcription

1 Logic-Leve Gate Drive dvanced Process Technoogy Surface Mount (IRL3303S) Low-profie through-hoe (IRL3303L) 75 C Operating Temperature Fast Switching Fuy vaanche Rated Description PD B IRL3303S/L HEXFET Power MOSFET 2 D Pak TO-262 V DSS = 30V R DS(on) = 0.026Ω I D = 38 Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The D 2 Pak is a surface mount power package capabe of accommodating die sizes up to HEX-4. It provides the highest power capabiity and the owest possibe onresistance in any existing surface mount package. The D 2 Pak is suitabe for high current appications because of its ow interna connection resistance and can dissipate up to 2.0W in a typica surface mount appication. The through-hoe version (IRL3303L) is avaiabe for owprofie appications. bsoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 38 I T C = 0 C Continuous Drain Current, V V 27 I DM Pused Drain Current 40 P = 25 C Power Dissipation 3.8 W P C = 25 C Power Dissipation 68 W Linear Derating Factor 0.45 W/ C V GS Gate-to-Source Votage ±6 V E S Singe Puse vaanche Energy 30 mj I R vaanche Current 20 E R Repetitive vaanche Energy 6.8 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Sodering Temperature, for seconds 300 (.6mm from case ) Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 2.2 C/W R θj Junction-to-mbient ( PCB Mounted,steady-state)** 40 G D S 8/25/97

2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 30 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Votage Temp. Coefficient V/ C Reference to 25 C, I D = m R DS(on) Static Drain-to-Source On-Resistance V GS = V, I D = Ω V GS = 4.5V, I D = 7 T J = 50 C V GS(th) Gate Threshod Votage.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 2 S V DS = 25V, I D = 20 I DSS Drain-to-Source Leakage Current 25 V DS = 30V, V GS = 0V µ 250 V DS = 24V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 6V n Gate-to-Source Reverse Leakage -0 V GS = -6V Q g Tota Gate Charge 26 I D = 20 Q gs Gate-to-Source Charge 8.8 nc V DS = 24V Q gd Gate-to-Drain ("Mier") Charge 5 V GS = 4.5V, See Fig. 6 and 3 t d(on) Turn-On Deay Time 7.4 V DD = 5V t r Rise Time 200 I D = 20 t d(off) Turn-Off Deay Time 4 R G = 6.5Ω t f Fa Time 36 R D = 0.7Ω, See Fig. L S Interna Source Inductance 7.5 nh Between ead, and center of die contact C iss Input Capacitance 870 V GS = 0V C oss Output Capacitance 340 pf V DS = 25V C rss Reverse Transfer Capacitance 70 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 38 (Body Diode) showing the I SM Pused Source Current integra reverse G 40 (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 20, V GS = 0V t rr Reverse Recovery Time 72 ns T J = 25 C, I F = 20 Q rr Reverse Recovery Charge µc di/dt = 0/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) ƒ I SD 20, di/dt 40/µs, V DD V (BR)DSS, T J 75 C V DD = 5V, starting T J = 25 C, L = 470µH Puse width 300µs; duty cyce 2%. R G = 25Ω, I S = 20. (See Figure 2) Uses IRL3303 data and test conditions. ** When mounted on " square PCB ( FR-4 or G- Materia ). For recommended footprint and sodering techniques refer to appication note #N-994.

3 I, D rain-to-source Current () D 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 V DS, Drain-to-Source Votage (V) I, D rain-to-source Current () D 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 75 C 0. 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-S ource C urrent ( ) 00 0 T = 25 C J V DS= 5V 20µs PULSE WIDTH V GS T = 75 C J, Gate-to-Source Votage (V) Fig 3. Typica Transfer Characteristics R DS(on), Drain-to-S ource On Resistance (Normaized) I D = 34 V GS = V T J, Junction Temperature ( C) Fig 4. Normaized On-Resistance Vs. Temperature

4 C, Capacitance (pf) V GS = 0V, f = M Hz C iss = C gs C gd, C ds SHORTE D C rss = C gd C is s C oss = C ds C gd C oss C rss 0 0 V DS, Drain-to-Source Votage (V) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage V GS, Gate-to-Source Votage (V) I D = 20 V DS = 24V V DS = 5V FOR TEST CIRCUIT SEE FIGURE Q, Tota Gate Charge (nc) G Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J I D, Drain Current () 00 0 OPE RTION IN THIS RE LIMITE D BY RDS(on) µs 0µs ms V GS = 0V V SD, Source-to-Drain Votage (V) T ms C = 25 C T J = 75 C Singe Puse 0 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating rea

5 I D, Drain Current () Fig a. Switching Time Test Circuit V DS 90% R G V GS 4.5V V DS Puse Width µs Duty Factor 0. % D.U.T. - V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) 0. D = SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t Peak T J = P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t 2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case

6 L V DS D.U.T. R G V - DD V I S t p 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS t p V DD E S, Singe Puse vaanche Energy (mj) I D TOP B OT TOM 20 V DD = 5V Starting T J, Junction Temperature ( C) V DS I S Fig 2b. Uncamped Inductive Waveforms Fig 2c. Maximum vaanche Energy Vs. Drain Current Current Reguator Same Type as D.U.T. 50KΩ V Q GS Q G Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3m Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Peak Diode Recovery dv/dt Test Circuit IRL3303S/L D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFETS

8 D 2 Pak Package Outine.40 (.055) MX..54 (.45).29 (.405) (.85) 4.20 (.65) - B -.32 (.052).22 (.048).6 (.400) RE F (.255) 6.8 (.243).78 (.070).27 (.050) (.6) 4.73 (.580) 2.79 (.) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.3) 2.32 (.09) 3X.40 (.055).4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) RE F (.0) M B M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIONS FTER SOLDER DIP. 2 DIMENSIONING & TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION : INCH. 4 HETSINK & LED DIMENSIONS DO NOT INCLUDE BURRS. LED SSIGNMENTS - G TE 2 - DR IN 3 - S OU RC E 8.89 (.350) 3.8 (.50) 7.78 (.700) 2.08 (.082) 2X 2.54 (.0) 2X Part Marking Information D 2 Pak IN TER NTION L RECTIFIER LOGO SSEMBLY LOT CODE F530S B M PRT NUMBER DTE CODE (YYWW ) YY = YER WW = WEEK

9 Package Outine TO-262 Outine Part Marking Information TO-262

10 Tape & Ree Information D 2 Pak TRR.60 (.063).50 (.059) 4. (.6) 3.90 (.53).60 (.063).50 (.059) (.045) (.035) FEED DIRECTION TRL.85 (.073).65 (.065).90 (.429).70 (.42).60 (.457).40 (.449) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) (.957) (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) (.079) (.94) (4.73) M X (2.362) MIN. NOTES :. CO MFOR MS TO EI CO NTRO LLING DIMENSION: MILLIMETER. 3. DIMENSIO N HUB. 4. INCLUDES FLNGE OUTER EDGE (.039) (.96) (.97) M X. 4 WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, Te: (3) EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Te: IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 2Z8, Te: (905) IR GERMNY: Saaburgstrasse 57, 6350 Bad Homburg Te: IR ITLY: Via Liguria 49, 07 Borgaro, Torino Te: IR FR EST: K&H Bdg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 7 Te: IR SOUTHEST SI: 35 Outram Road, #-02 Tan Boon Liat Buiding, Singapore 036 Te: Data and specifications subject to change without notice. 8/97

11 Note: For the most current drawings pease refer to the IR website at: