V DSS R DS(on) max Qg

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1 l pplication Specific MOSFETs l Ideal for CPU Core C-C Converters l Low Conduction Losses l Low Switching Losses l Low Profile (<0.7 mm) l ual Sided Cooling Compatible l Compatible with existing Surface Mount Techniques IRF6604 HEXFET Power MOSFET irectfet ISOMETRIC escription The IRF6604 combines the latest HEXFET Power MOSFET Silicon technology with the advanced irectfet TM packaging to achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm profile. The irectfet package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note N-1035 is followed regarding the manufacturing methods and process. The irectfet package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%. The IRF6604 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency C-C converters that power the latest generation of processors operating at higher frequencies. The IRF6604 has been optimized for parameters that are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket. Notes through ˆ are on page /16/05 MQ pplicable irectfet Outline and Substrate Outline (see p.9,10 for details) bsolute Maximum Ratings Parameter Max. Units V S rain-to-source Voltage 30 V V GS Gate-to-Source Voltage ±12 T C = 25 C Continuous rain Current, V 7.0V 49 T = 25 C Continuous rain Current, V 7.0V 12 T = 70 C Continuous rain Current, V 7.0V 9.2 I M Pulsed rain Current c 92 = 25 C Power issipation g 2.3 = 70 C Power issipation g 1.5 W C = 25 C Power issipation 42 Linear erating Factor W/ C T J Operating Junction and -40 to 150 C Storage Temperature Range T STG SQ SX ST MQ MX MT P E V SS R S(on) max Qg 30V 11.5mΩ@V GS = 7.0V 17nC 13mΩ@V GS = 4.5V Thermal Resistance Parameter Typ. Max. Units R θj Junction-to-mbient fj 55 R θj Junction-to-mbient gj 12.5 R θj Junction-to-mbient hj 20 C/W R θjc Junction-to-Case ij 3.0 R θj-pcb Junction-to-PCB Mounted 1.0

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV SS rain-to-source Breakdown Voltage 30 V ΒV SS / T J Breakdown Voltage Temp. Coefficient 27 mv/ C R S(on) Static rain-to-source On-Resistance mω V GS = 4.5V, I = 9.6 e V GS(th) Gate Threshold Voltage V V S = V GS, I = 250µ V GS(th) / T J Gate Threshold Voltage Coefficient -4.5 mv/ C I SS rain-to-source Leakage Current 30 µ V S = 24V, V GS = 0V 50 µ V S = 30V, V GS = 0V 100 V S = 24V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 100 n V GS = 12V Gate-to-Source Reverse Leakage -100 V GS = -12V gfs Forward Transconductance 38 S V S = 15V, I = 9.6 Q g Total Gate Charge Q gs1 Pre-Vth Gate-to-Source Charge 4.1 V S = 15V Q gs2 Post-Vth Gate-to-Source Charge 1.0 nc V GS = 4.5V Q gd Gate-to-rain Charge 6.3 I = 9.6 Q godr Gate Charge Overdrive 5.6 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 7.3 Q oss Output Charge 9.5 nc V S = 16V, V GS = 0V R G Gate Resistance Ω t d(on) Turn-On elay Time 11 V = 15V, V GS = 4.5Ve t r Rise Time 4.3 I = 9.6 t d(off) Turn-Off elay Time 18 ns Clamped Inductive Load t f Fall Time 25 C iss Input Capacitance 2270 V GS = 0V C oss Output Capacitance 420 pf V S = 15V C rss Reverse Transfer Capacitance 190 ƒ = 1.0MHz valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energyd 32 mj I R valanche Currentc 9.6 E R Repetitive valanche Energy c 0.23 mj iode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 42 (Body iode) I SM Pulsed Source Current 92 (Body iode)c V S iode Forward Voltage V t rr Reverse Recovery Time ns Q rr Reverse Recovery Charge nc Conditions V GS = 0V, I = 250µ Reference to 25 C, I = 1m V GS = 7.0V, I = 12 e Conditions MOSFET symbol showing the G integral reverse S p-n junction diode. T J = 25 C, I S = 9.6, V GS = 0V e T J = 25 C, I F = 9.6 di/dt = 100/µs e 2

3 I, rain-to-source Current (Α) I, rain-to-source Current () I, rain-to-source Current () IRF VGS TOP 10V 7.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V VGS TOP 10V 7.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V 2.7V 2.7V µs PULSE WITH Tj = 25 C V S, rain-to-source Voltage (V) 1 20µs PULSE WITH Tj = 150 C V S, rain-to-source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics T J = 150 C 2.0 I = 12 T J = 25 C V S = 15V 20µs PULSE WITH V GS, Gate-to-Source Voltage (V) R S(on), rain-to-source On Resistance (Normalized) V GS = 7.0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I, rain-to-source Current () C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF Ciss V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTE C rss = C gd C oss = C ds C gd I = 9.6 V S = 24V V S = 15V 1000 Coss Crss V S, rain-to-source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. rain-to-source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERTION IN THIS RE LIMITE BY R S (on) I S, Reverse rain Current () T = 150 J C 10 T = 25 J C 1 V GS= 0 V V S,Source-to-rain Voltage (V) Tc = 25 C Tj = 150 C Single Pulse 100µsec 1msec 10msec V S, rain-tosource Voltage (V) Fig 7. Typical Source-rain iode Forward Voltage Fig 8. Maximum Safe Operating rea 4

5 V GS(th) Gate threshold Voltage (V) IRF I, rain Current () I = 250µ T, mbient Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum rain Current Vs. mbient Temperature Fig 10. Threshold Voltage Vs. Temperature 100 Thermal Response (Z thj ) 10 1 = SINGLE PULSE (THERML RESPONSE) 2. Peak T J = P M x Z thj T t 1, Rectangular Pulse uration (sec) Notes: 1. uty factor = t 1 / t 2 P M t 1 t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-mbient 5

6 R G V S 20V V GS tp L.U.T IS 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp 15V RIVER - V V (BR)SS E S, Single Pulse valanche Energy (mj) TOP BOTTOM I Starting Tj, Junction Temperature ( C) Fig 12c. Maximum valanche Energy Vs. rain Current I S Fig 12b. Unclamped Inductive Waveforms V S L V - Current Regulator Same Type as.u.t. V GS Pulse Width < 1µs uty Factor < 0.1%.U.T 50KΩ 12V.2µF.3µF Fig 14a. Switching Time Test Circuit.U.T. V - S V S 90% V GS 3m 10% I G I Current Sampling Resistors Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 V GS t d(on) t r t d(off) t f

7 -.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current river Gate rive Period P.W..U.T. I S Waveform Body iode Forward Current di/dt.u.t. V S Waveform iode Recovery dv/dt = P.W. Period V GS =10V V * R G dv/dt controlled by RG river same type as.u.t. I S controlled by uty Factor "".U.T. - evice Under Test V - Re-pplied Voltage Inductor Curent Body iode Forward rop Ripple 5% I S * V GS = 5V for Logic Level evices Fig 15. Peak iode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform 7

8 Power MOSFET Selection for Non-Isolated C/C Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f i g ( ) Q g V g f Q oss 2 V f in I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q1. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. s Q1 turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure : Q oss Characteristic 8

9 irectfet Outline imension, MQ Outline (Medium Size Can, Q-esignation). Please see irectfet application note N-1035 for all details regarding the assembly of irectfet. This includes all recommendations for stencil and substrate designs. COE B C E F G H J K L M N P Ã IMENSIONS METRIC MX IMPERIL ÃMX

10 irectfet Substrate and PCB Layout, MQ Outline (MediumSize Can, Q-esignation). Please see irectfet application note N-1035 for all details regarding the assembly of irectfet. This includes all recommendations for stencil and substrate designs. G = GTE = RIN S = SOURCE G S S 10

11 irectfet Tape & Reel imension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6604). For 1000 parts on 7" reel, order IRF6604TR1 COE B C E F G H REEL IMENSIONS STNR OPTION (QTY 4800) TR1 OPTION (QTY 1000) METRIC IMPERIL METRIC IMPERIL MX MX MX MX LOE TPE FEE IRECTION COE B C E F G H IMENSIONS METRIC IMPERIL MX MX

12 irectfet Part Marking Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.70mH R G = 25Ω, I S = 9.6. ƒ Pulse width 400µs; duty cycle 2%. Surface mounted on 1 in. square Cu board. Used double sided cooling, mounting pad. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. T C measured with thermal couple mounted to top (rain) of part. ˆ R θ is measured at T J of approximately 90 C. ata and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORL HEQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (310) TC Fax: (310) Visit us at for sales contact information. 11/

13 Note: For the most current drawings please refer to the IR website at: