V DSS V GS R DS(on) R DS(on) Q g tot Q gd Q gs2 Q rr Q oss V gs(th)

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1 Typical R S(on) (m ) RoHs Compliant Containing No Lead and Bromide Integrated Monolithic Schottky iode Low Profile (<0.7 mm) ual Sided Cooling Compatible Low Package Inductance Optimized for High Frequency Switching Ideal for CPU Core C-C Converters Optimized for Sync. FET socket of Sync. Buck Converter Low Conduction and Switching Losses Compatible with existing Surface Mount Techniques % Rg tested IRF6894MPbF IRF6894MTRPbF HEXFET Power MOSFET plus Schottky iode Typical values (unless otherwise specified) V SS V GS R S(on) R S(on) 25V min ±6V max 4.5V Q g tot Q gd Q gs2 Q rr Q oss V gs(th) 3nC nc 3.0nC 58nC 33nC.6V G Footprint compatible to irectfet S S Applicable irectfet Outline and Substrate Outline (see p.7,8 for details) MX irectfet ISOMETRIC SQ SX ST MQ MX MT MP escription The IRF6894MPbF combines the latest HEXFET Power MOSFET Silicon technology with the advanced irectfet packaging to achieve the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The irectfet package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques. Application note AN-35 is followed regarding the manufacturing methods and processes. The irectfet package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%. The IRF6894MPbF balances industry leading on-state resistance while minimizing gate charge along with low gate resistance to reduce both conduction and switching losses. This part contains an integrated Schottky diode to reduce the Qrr of the body drain diode further reducing the losses in a Synchronous Buck circuit. The reduced losses make this product ideal for high frequency/high efficiency C-C converters that power high current loads such as the latest generation of microprocessors. The IRF6894MPbF has been optimized for parameters that are critical in synchronous buck converter s Sync FET sockets. Standard Pack Base part number Package Type Orderable Part Number Form Quantity IRF6894MTRPbF irectfet Medium Can Tape and Reel 4800 IRF6894MTRPbF Absolute Maximum Ratings Parameter Max. Units V S rain-to-source Voltage 25 V GS Gate-to-Source Voltage ±6 V T A = 25 C Continuous rain Current, V V (Silicon Limited) 37 T A = 70 C Continuous rain Current, V V (Silicon Limited) 29 T C = 25 C Continuous rain Current, V V (Silicon Limited) 63 A I M Pulsed rain Current 296 E AS Single Pulse Avalanche Energy 540 mj I AR Avalanche Current 30 A I = 37A T J = 25 C V GS, Gate-to-Source Voltage (V) I = 30A V S = 20V V S = 3V VS= 5V T J = 25 C Q G Total Gate Charge (nc) V GS, Gate -to -Source Voltage (V) Fig. Typical On-Resistance vs. Gate Voltage Notes Click on this section to link to the appropriate technical paper. Click on this section to link to the irectfet Website. Surface mounted on in. square Cu board, steady state. Fig 2. Typical Total Gate Charge vs. Gate-to-Source Voltage TC measured with thermocouple mounted to top (rain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L =.2mH, R G = 50, I AS = 30A

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BV SS rain-to-source Breakdown Voltage 25 V V GS = 0V, I =.0mA V SS / T J Breakdown Voltage Temp. Coefficient 0.02 V/ C I = ma (25 C-25 C) R S(on) Static rain-to-source On-Resistance V GS = V, I = 37A m.4.8 V GS = 4.5V, I = 30A V GS(th) Gate Threshold Voltage V V S = V GS, I = µa V GS(th) / T J Gate Threshold Voltage Temp. Coefficient -3.8 mv/ C V S = V GS, I = ma I SS rain-to-source Leakage Current 500 µa V S = 20 V, V GS = 0V Gate-to-Source Forward Leakage V GS = 6V I GSS na Gate-to-Source Reverse Leakage - V GS = -6V gfs Forward Transconductance 93 S V S = 3V, I = 30A Q g Total Gate Charge 3 47 Q gs Pre Vth Gate-to-Source Charge 8. V S = 3V Q gs2 Post Vth Gate-to-Source Charge 3.0 V GS = 4.5V nc Q gd Gate-to-rain Charge I = 30A Q godr Gate Charge Overdrive See Fig 5 Q sw Switch Charge (Q gs2 + Q gd) 3 Q oss Output Charge 33 nc V S = 6V, V GS = 0V R G Gate Resistance 0.2 t d(on) Turn-On elay Time 7 V = 3V, V GS = 4.5V t r Rise Time 47 I = 30A ns t d(off) Turn-Off elay Time 23 R G =.8 t f Fall Time 3 See Fig 7 C iss Input Capacitance 4232 V GS = 0V C oss Output Capacitance 260 pf V S = 3V C rss Reverse Transfer Capacitance 255 ƒ =.0MHz iode Characteristics I S I SM Parameter Min. Typ. Max. Units Conditions Continuous Source Current MOSFET symbol 37 (Body iode) showing the G A Pulsed Source Current integral reverse 296 (Body iode) p-n junction diode. V S iode Forward Voltage 0.75 V T J = 25 C, I S = 30A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 30A Q rr Reverse Recovery Charge nc di/dt = 320A/µs S Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400µs; duty cycle 2%

3 Absolute Maximum Ratings Symbol Parameter Max. Units A = 25 C Power issipation 2.8 A = 70 C Power issipation.8 W C = 25 C Power issipation 54 T P Peak Soldering Temperature 270 T J Operating Junction and -40 to + 50 Storage Temperature Range C T STG Thermal Resistance Symbol Parameter Typ. Max. Units R JA Junction-to-Ambient 45 R JA Junction-to-Ambient 2.5 R JA Junction-to-Ambient 20 C/W R JC Junction-to-Can 2.3 R JA-PCB Junction-to-PCB Mounted.0 Linear erating Factor W/ C Thermal Response ( Z thja ) = SINGLE PULSE ( THERMAL RESPONSE ) Notes:. uty Factor = t/t2 2. Peak Tj = P dm x Zthja + Tc E-006 E t, Rectangular Pulse uration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Notes: Surface mounted on in. square Cu board, steady state. T C measured with thermocouple incontact with top (rain) of part. Used double sided cooling, mounting pad with large heatsink. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. R is measured at T J of approximately 90 C. Surface mounted on in. square Cu board (still air). Mounted to a PCB with small clip heatsink (still air) Mounted on minimum footprint full size board with metalized back and with small clip heatsink (still air)

4 C, Capacitance(pF) Typical R S (on) (m ) I, rain-to-source Current(A) Typical R S(on) (Normalized) I, rain-to-source Current (A) I, rain-to-source Current (A) IRF6894MTRPbF 0 0 VGS TOP V 2.5V 5.0V 4.5V 3.5V 3.3V 3.0V 2.8V 60µs PULSE WITH BOTTOM 2.5V Tj = 25 C V S, rain-to-source Voltage (V) Fig 4. Typical Output Characteristics 2.5V VGS TOP V 5.0V 4.5V 3.5V 3.3V 3.0V 2.8V 60µs PULSE WITH BOTTOM 2.5V Tj = 50 C 0. V S, rain-to-source Voltage (V) Fig 5. Typical Output Characteristics 0 T J = 50 C T J = 25 C T J = -40 C.6.4 I = 37A V GS = V V GS = 4.5V.2.0 V S = 5V 60µs PULSE WITH V GS, Gate-to-Source Voltage (V) Fig 6. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 7. Normalized On-Resistance vs. Temperature V GS = 0V, f = MHZ C iss = C gs + C gd, C ds SHORTE C rss = C gd C oss = C ds + C gd C oss C iss T J = 25 C Vgs = 3.5V Vgs = 4.5V Vgs = 5.0V Vgs = 7.0V Vgs = 8.0V Vgs = V Vgs = 2V Vgs = 5V 0 C rss V S, rain-to-source Voltage (V) Fig 8. Typical Capacitance vs. rain-to-source Voltage I, rain Current (A) Fig 9. Typical On-Resistance vs. rain Current and Gate Voltage

5 I, rain Current (A) I S, Reverse rain Current (A) E AS, Single Pulse Avalanche Energy (mj) Typical V GS(th) Gate threshold Voltage (V) IRF6894MTRPbF OPERATION IN THIS AREA LIMITE BY R S (on) µsec msec msec T J = 50 C T J = 25 C T J = -40 C V GS = 0V V S, Source-to-rain Voltage (V) I, rain-to-source Current (A) T 0. A = 25 C C Tj = 50 C Single Pulse V S, rain-tosource Voltage (V) Fig. Typical Source-rain iode Forward Voltage Fig. Maximum Safe Operating Area I = ma T C, Case Temperature ( C) T J, Temperature ( C ) Fig 2. Maximum rain Current vs. Case Temperature Fig 3. Typical Threshold Voltage vs. Junction Temperature I TOP 2.0A 3.0A BOTTOM 30A Starting T J, Junction Temperature ( C) Fig 4. Maximum Avalanche Energy vs. rain Current

6 Fig 5a. Gate Charge Test Circuit Fig 5b. Gate Charge Waveform Fig 6a. Unclamped Inductive Test Circuit Fig 6b. Unclamped Inductive Waveforms Fig 7a. Switching Time Test Circuit Fig 7b. Switching Time Waveforms

7 Fig 8. iode Reverse Recovery Test Circuit for HEXFET Power MOSFETs irectfet Board Footprint, MX Outline (Medium Size Can, X-esignation). Please see irectfet application note AN-35 for all details regarding the assembly of irectfet. This includes all recommendations for stencil and substrate designs. G=GATE =RAIN S=SOURCE G S S Note: For the most current drawing please refer to website at

8 irectfet Outline imension, MX Outline (Medium Size Can, X-esignation). Please see irectfet application note AN-35 for all details regarding the assembly of irectfet. This includes all recommendations for stencil and substrate designs. COE A B C E F G H J K L M R P IMENSIONS METRIC IMPERIAL MIN MAX MIN MAX irectfet Part Marking Note: For the most current drawing please refer to website at

9 irectfet Tape & Reel imension (Showing component orientation). Note: For the most current drawing please refer to website at

10 Qualification Information Qualification Level Industrial Moisture Sensitivity Level RoHS Compliant irectfet Medium Can MSL (per JEEC J-ST-020 ) Yes Applicable version of JEEC standard at the time of product release. Revision History ate /3/206 Comment Changed datasheet with Infineon logo all pages. Changed Rth from 60 C/W to 45 C/W page 3 Changed TA 25C/70C from 32A/25A to 37A/29A page & 2. Changed Fig. to Fig.5 page to 9. Added disclaimer on last page. Published by Infineon Technologies AG 8726 München, Germany Infineon Technologies AG 205 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( WARNINGS ue to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury