EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design 2009 Page 1. EE247 Lecture 18

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1 EE247 Lecture 8 ADC Converters Sampling (continued) Bottom-plate switching Track & hold T/H circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H aperture uncertainty ADC architectures and design Serial- slope type Successive approximation Flash ADC and its sources of error: comparator offset, sparkle code & meta-stability EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page EE247 Lecture 8 Administrative issues Midterm exam on Thurs. Nov. 5th o You can only bring one 8x paper with your own written notes (please do not photocopy) o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones... o Midterm includes material covered to end of lecture 4 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 2

2 Avoiding Switch Charge Injection Bottom Plate Sampling φ D φ M V H V i Cs V O V L φ D φ M2 t Switches M2 opened slightly earlier compared to M Injected charge due to turning off M2 is constant since its GS voltage is constant & eliminated when used differentially Since C s bottom plate is already open when M is switched off: No signal dependant charge injected on C s EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 3 Flip-Around Track & Hold φ 2 φ S2A φ D φ D φ 2 v IN φ D C φ 2 S3 SA S2 v OUT φ S Concept based on bottomplate sampling v CM EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 4

3 Flip-Around T/H-Basic Operation φ high φ 2 φ S2A φ D φ D φ 2 v IN φ D SA C φ 2 S2 S3 Charging C vout Q φ =V IN xc φ S v CM Note: Opamp has to be stable in unity-gain configuration EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 5 Flip-Around T/H-Basic Operation φ 2 high φ 2 φ S2A φ D φ D φ 2 φ D C φ 2 S3 Holding v IN SA S2 v OUT φ S v CM Q φ2 =V OUT xc V OUT = V IN EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 6

4 Flip-Around T/H - Timing φ 2 S2A φ D φ φ D v IN φ D C φ 2 S3 φ 2 SA φ S S2 v CM vout S opens earlier than SA No resistive path from C bottom plate to Gnd charge can not change "Bottom Plate Sampling" EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 7 Charge Injection At the instant of transitioning from track to hold mode, some of the charge stored in sampling switch S is dumped onto C With "Bottom Plate Sampling", only charge injection component due to opening of S and is to first-order independent of v IN Only a dc offset is added. This dc offset can be removed with a differential architecture EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 8

5 Flip-Around T/H Constant switch V GS to minimize distortion φ 2 φ S2A φ D φ D φ 2 v IN φ D SA C φ 2 S2 S3 v OUT φ S v CM Note: Among all switches only SA & S2A experience full input voltage swing EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 9 Flip-Around T/H S is chosen to be an n-channel MOSFET Since it always switches the same voltage, it s onresistance, R S, is signal-independent (to first order) Choosing R S >> R SA minimizes the non-linear component of R = R SA + R S Typically, SA is a wide (much lower resistance than S) & constant V GS switch In practice size of SA is limited by the (nonlinear) S/D capacitance that also adds distortion If SA s resistance is negligible delay depends only on S resistance S resistance is independent of V IN error due to finite time-constant independent of V IN EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page

6 Differential Flip-Around T/H Choice of Sampling Switch Size C s =7pF THD simulated w/o sampling switch boosted clock -45dB THD simulated with sampling switch boosted clock (see graph) Ref: K. Vleugels et al, A 2.5-V Sigma Delta Modulator for Broadband Communications Applications IEEE JSSC, VOL. 36, NO. 2, DECEMBER 2, pp. 887 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page Differential Flip-Around T/H S S2 Offset voltage associated with charge injection of S & S2 cancelled by differential nature of the circuit During input sampling phase amp outputs shorted together Ref: W. Yang, et al. A 3-V 34-mW 4-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 2, DECEMBER 2 93 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 2

7 Differential Flip-Around T/H Gain= Feedback factor= φ φ φ2 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 3 Differential Flip-Around T/H Issues: Input Common-Mode Range.7V VCM=.5V V V V.5V.2V.3V.8V ΔV in-cm =-.5= -.5V ΔV in-cm =V out_com -V sig_com Drawback: Amplifier needs to have large input common-mode compliance EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 4

8 Input Common-Mode Cancellation Note: Shorting switch M3 added Ref: R. Yen, et al. A MOS Switched-Capacitor Instrumentation Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-7, NO. 6,, DECEMBER EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 5 Input Common-Mode Cancellation V+.2V V-.2V Track mode (φ high) V C =V I, V C2 =V I2 V o =V o2 = Hold mode (φ low) V o +V o2 = V o -V o2 = -(V I -V I2 )(C /(C +C 3 )) Input common-mode level removed EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 6

9 Switched-Capacitor Techniques Combining Track & Hold with Other Functions T/H + Charge redistribution amplifier T/H & Input difference amplifier T/H & summing amplifier Differential T/H combined with gain stage Differential T/H including offset cancellation EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 7 T/H + Charge Redistribution Amplifier Track mode: (S, S3 on S2 off) V C =V os V IN, V C2 = V o =V os EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 8

10 T/H + Charge Redistribution Amplifier Hold Mode 2 Hold/amplify mode (S, S3 off S2 on) Offset NOT cancelled, but not amplified Input-referred offset =(C 2 /C ) x V OS, & often C 2 <C EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 9 T/H & Input Difference Amplifier Sample mode: (S, S3 on S2 off) V C =V os V I, V C2 = V o =V os EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 2

11 Input Difference Amplifier Cont d Subtract/Amplify mode (S, S3 off S2 on) During previous phase: V C =V os V I, V C2 = V o =V os Offset NOT cancelled, but not amplified Input-referred offset =(C 2 /C )xv OS, & C 2 <C EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 2 T/H & Summing Amplifier EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 22

12 T/H & Summing Amplifier Cont d Sample mode (S, S3, S5 on S2, S4 off) V C =V os V I, V C2 =V os -V I3, V C3 = V o =V os EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 23 T/H & Summing Amplifier Cont d Amplify mode (S, S3, S5 off, S2, S4 on) 3 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 24

13 Differential T/H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opamp Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 987 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 25 Differential T/H Combined with Gain Stage φ High Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 987 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 26

14 Differential T/H Combined with Gain Stage Gain=4C/C=4 Input voltage common-mode level removed opamp can have low input common-mode compliance Amplifier offset NOT removed Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 987 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 27 Differential T/H Including Offset Cancellation Operation during offset cancellation phase shown Auxilary inputs added with A main /A aux.= During offset cancellation phase: Aux. amp configured in unity-gain mode: offset stored on C AZ & canceled during the signal acquisition phase Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 3-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp , December 987. EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 28

15 Differential T/H Including Offset Cancellation Operational Amplifier Operational amplifier dual input folded-cascode opamp M3,4 auxiliary input, M,2 main input To achieve / gain ratio W M3, 4 =/x W M,2 & current sources are scaled by / M5,6,7 common-mode control Output stage dual cascode high DC gain V out =g m,2 r o V in + g m3,4 r o V in2 Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 3-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp , December 987. EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 29 Differential T/H Including Offset Cancellation Phase + - (V INAZ+ -V INAZ- )= -g m,2 /g m3,4 V offset V offset During offset cancellation phase AZ and S closed main amplifier offset amplified by g m /g m2 & stored on C AZ Auxiliary amp chosen to have lower gain so that: Aux. amp charge injection associated with opening of switch AZ reduced by A aux /A main =/ Insignificant increase in power dissipation resulting from addition of aux. inputs Requires an extra auto-zero clock phase EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 3

16 V V CLK Track & Hold Aperture Time Error V CLK x V in +V TH V in M V O x V in C s x Time Transition from track to hold: Occurs when device turns fully off V CLK =V in +V TH Sharp fall-time wrt signal change no aperture error EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 3 V x V CLK x x Track & Hold Aperture Time Error V in +V TH V in Time Slow falling clock aperture error V in =A sin(2π f in t) ε= f in xax t fall /V CLK SDR= - 2logε -4[dB] (imperical see Ref.) Example: Nyquist rate -bit ADC & A=V CLK /4 SQNR=62dB for distortion due to aperture error < quant noise t fall < 2x -3 /f in Worst case: f in = f s /2 t fall < 4x -3 /f s e.g. f s =MHz, t fall <4psec Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp , April 99. EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 32

17 Track & Hold Aperture Time Error Aperture error analysis applies to simple sampling network Bottom plate sampling minimizes aperture error Boosted clock reduces aperture error Clock edge fall/rise trade-off between switch charge injection versus aperture error Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp , April 99. EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 33 ADC Architecture & Design EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 34

18 ADC Architectures Slope type converters Successive approximation Flash Time-interleaved / parallel converter Folding Residue type ADCs Two-step Pipeline Oversampled ADCs EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 35 Various ADC Architectures Resolution/Conversion Rate Resolution Oversampled & Serial Algorithmic e.g. Succ. Approx. Subranging e.g. Pipelined Folding & Interpolative Parallel & Time Interleaved Conversion Rate EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 36

19 Serial ADC Single Slope V Ramp Ramp Generator V Ramp V IN "" stop start B....B N.. Counter Clock Time Counter starts V Ramp = Counter stops counting for V IN =V Ramp EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 37 Serial ADC Single Slope V Ramp V IN Ramp Generator V Ramp V IN "" stop start B....B N.. Counter Clock T Time Note that dt is proportional to V IN Counter output proportional to T=nT clock Counter output proportional to V IN 2 N xt clock = V FS EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 38

20 Single Slope ADC Advantages: Low complexity & simple INL depends on ramp linearity & not component matching Inherently monotonic Disadvantages: Slow (2 N clock pulses for N-bit conversion) (e.g. N=6 f clock =MHz needs 65xμs=65ms/conversion) Hard to generate precise ramp required for high resolution ADCs Need to calibrate ramp slope versus V IN Better: Dual Slope, Multi-Slope EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 39 Serial ADC Dual Slope V IN V "" Integrator o -V REF Flip Flop Clock B..B N.. Counter & Timing First: V IN is integrated for a fixed time (2 N xt CLK ) V o = 2 N xt CLK V IN /τ intg Next: V o is de-integrated with V REF until V o = Counter output = 2 N V IN /V REF EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 4

21 Dual Slope ADC Slope α V IN Slope = Const. Integrate V in for fixed time (T INT ), de-integrate with V REF applied T De-Int ~ 2 Nx T CLK xv in /V REF Most laboratory DVMs use this type of ADC EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 4 Dual Slope ADC Advantage: Accuracy to st order independent of integrator time-constant and clock period Comparator offset referred to input is attenuated by integrator high DC gain Insensitive to most linear error sources DNL is a function of clock jitter Power line (6Hz) xtalk effect on reading can be canceled by: choosing conversion time multiple of /6Hz High accuracy achievable (6+bit) Disadvantage: Slow (maximum 2x2 N xt clk per conversion) Integrator opamp offset results in ADC offset (can cancel) Finite opamp gain gives rise to INL EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 42

22 Successive Approximation ADC SAR Algorithmic type ADC Based on binary search over DAC output Reset DAC Set DAC[MSB]= V IN T/H MSB Y V IN >V DAC? N MSB V REF DAC Set DAC[MSB-]= Control Logic Clock [MSB-] [LSB] Y Y V IN >V DAC?. V IN >V DAC? N [MSB-] N [LSB] DAC[Input]= ADC[Output] EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 43 Successive Approximation ADC Example: 6-bit ADC & V IN =5/8V REF V IN T/H V REF Control Logic Clock DAC + - 3/4 5/8 /2 V DAC /V REF /2 3/4 5/8 /6 2/32 4/64 V IN DAC Output Test MSB Test MSB- ADC Time / Clock Ticks High accuracy achievable (6+ Bits) Required N clock cycles for N-bit conversion (much faster than slope type) Moderate speed (highest SAR conversion rate 2Ms/sec & 8bits) EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 44

23 Example: SAR ADC Charge Redistribution Type S top Comparator 32C 6C 8C 4C 2C C C - Out b 4 (MSB) b 3 b 3 b 2 b b V in Control To Logic switches V REF V in Built with binary weighted capacitors, switches, comparator & control logic T/H inherent in DAC EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 45 Charge Redistribution Type SAR DAC Operation: MSB 32C 32C 32C -V in +V REF /2 32C - Comparator Out b 4 (MSB) V in Phase b 3 -b V REF b 4 (MSB) b 3 -b Phase 2 To switches Control Logic Operation starts by connecting all top plate to gnd and all bottom plates to V in To test the MSB all top plate are opened bottom plate of 32C connected to V REF & rest of bottom plates connected to ground input to comparator= -V in +V REF /2 Comparator is strobed to determine the polarity of input signal: If negative MSB=, else MSB= The process continues until all bits are determined EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 46

24 Example: SAR ADC Charge Redistribution Type reset C P -Comparator 32C 6C 8C 4C 2C C C Out b 4 (msb) b 3 b 3 b 2 b b V in Control Logic To switches V REF V in To st order parasitic (C p ) insensitive since top plate driven from initial to final by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle (see Ref.) Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 5 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 9, pp , December 984. EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 47 B-bit flash ADC: DAC generates all possible 2 B - levels Flash ADC V REF V IN f s 2 B - comparators compare V IN to DAC outputs Comparator output: If V DAC < V IN If V DAC > V IN Comparator outputs form thermometer code D A C B - B Encoder Digital Output Encoder converts thermometer to binary code Application example: 6-bit Flash ADC in Disk Drives with Gs/s conversion rate + - EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 48

25 Flash ADC Converter Example: 3-bit Conversion V IN V IN V REF V REF f s Thermometer code Encoder Binary B-bits T s Time EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 49 Flash Converter Characteristics Very fast: only clock cycle per conversion ½ clock cycle V IN & V DAC comparison ½ clock cycle 2 B - to B encoding High complexity: 2 B - comparators V IN V REF f s Encoder Input capacitance of 2 B - comparators connected to the input node: High input node Thermometer code B-bits EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 5

26 Flash Converter Example: 8-bit ADC Design Considerations 8-bit 255 comparators R/2 V REF V IN f s V REF =V LSB=4mV R DNL</2LSB Comparator input referred offset < 2mV R R. Encoder Digital Output Assuming close to % yield, 2mV =6σ offset σ offset <.33mV R R/2 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 5 Flash ADC Converter Example: 8-bits ADC (continued) σ Offset <.33mV Let us assume in the technology used: Voffset-per-unit-sqrt(WxL)=3 mvx μ 3mV 2 V ffset = =.33mV W L= 83μ W L 2 2 Assuming: Cox = 9 ff/ μ CGS = CoxW L= 496 ff 3 Total max. input capacitance: = 26.5 pf! Issues: Si area quite large Large ADC input capacitance Since depending on input voltage level different number of comparator input transistors would be on/off- total input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp , October 989. EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 52

27 Flash ADC Converter Example (continued) Trade-offs: Allowing larger DNL e.g. LSB instead of.5lsb: Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduces the input capacitance by a factor of 4! Reducing the ADC resolution by -bit Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduce the input capacitance by a factor of 4 EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 53 Flash Converter Maximum Tolerable Comparator Offset versus ADC Resolution Assumption: DNL=.5LSB Note: Graph shows max. tolerable offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2σ to 6σ offset voltage Maximum Comparator V offset [mv] 2 - V REF =2V V REF =V ADC Resolution EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 54

28 R/2 R R R R R/2 V REF. Flash Converter Sources of Error V IN f s Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Feedthrough of input signal to reference ladder Kickback noise (disturbs reference) Signal dependent sampling time Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 55 Typical Flash Output Encoder V DD Thermometer code -of-n code b3 b2 b b Binary B-bits Thermometer to Binary encoder ROM Thermometer code -of-n decoding Final encoding NOR ROM Ideally, for each code, only one ROM row is on b3 b2 b b Output EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 56

29 Sparkle Codes V DD Erroneous (comparator offset?) b3 b2 b b Correct Output: Problem: Two rows are on Erroneous Output: Up to ~ ½ FS error!! EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 57 Sparkle Tolerant Encoder Protects against a single sparkle. Possible to improve level of sparkle protection by increasing # of NAND gate inputs Ref: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 58

30 Meta-Stability X Different gates interpret metastable output X differently Correct output: Erroneous output: Solutions: Latches (high power) Gray encoding Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 996, pp EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 59 Gray Encoding Example: 3bit ADC Thermometer Code Gray Binary T 7 T 6 T 5 T 4 T 3 T 2 T G 3 G 2 G B 3 B 2 B G = T T + T T G G = T T = T Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 6

31 Voltage Comparators V DD V i+ V i- + - V out (Digital Output) Play an important role in majority of ADCs Function: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference: If V i+ -V i- > V out = If V i+ -V i- < V out = EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 6 Voltage Comparator Architectures Comparator architectures: High gain amplifier with differential analog input & single-ended large swing output Output swing has to be compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe (clock edge), input stage disabled & digital output stored in a latch till next strobe Two options for implementation : Latch-only comparator Low-gain preamplifier + high-sensitivity latch Sampled-data comparators T/H input Offset cancellation EECS 247 Lecture 8: Data Converters- Track & Hold- ADC Design 29 Page 62