High Speed Flash Analog to Digital Converters

Transcription

1 ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec High Speed Flash Analog to Digital Converters Alireza Mahmoodi Abstract Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. They are suitable for high speed applications. However, flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. In this article we are going to discuss the methods to increase the performance of Flash ADCs. Index Terms Flash, ADC, Analog-to-digital conversion. T I. INTRODUCTION ODAY S high rate signal processing in various applications such as the read channels of hard disks, Gigabit Ethernet or optical communications rely on digital signal processing circuitry. These circuits require high speed ADCs to provide the interface between the analog and digital parts of the system. Flash ADCs are so faster than the other types of ADCs. For example a Flash ADCs can achieve 4GS/s with 6 bit resolution in a 0.13µm standard CMOS technology [1,2]. The main drawback of Flash ADC is its power consumption. In this report we will discuss different issues in designing a Flash ADC and find out how to improve its performance. In a Flash ADC a resistive divider with 2 N resistors provides 2 N -1 reference voltage. For an "N" bit converter, the circuit employs 2 N -1 comparators. The comparator will compare the input signal to a reference level and will calculate the output bit [3]. The output of the comparators is known as thermometer code. The thermometer code is then decoded to the appropriate digital output code. Figure (1) shows the structure of a flash ADC. Different methods have been introduced in order to achieve higher speed with lower power consumption. Next sections will discuss some of these methods. At the end, simulation results will be presented. II. TIMING ISSUES Clock generation and distribution is an important issue in high speed circuits. Since an uncertainty in clock (jitter) directly translates into reduction of the resolution of the system, Jitter has to be kept as small as possible [1]. Therefore an on chip low-jitter sampling clock source internally should be used. And The clock signal is distributed by means of an H-tree structure [1]. III. REDUCING MISMATCH BY DIGITALLY AVERAGIN Designing the comparator is the most difficult part. And all of the devices, especially in the first stage of the comparators should be sized accordingly to reduce mismatch in the input of the comparators. Device mismatch, because of process variation, causes an input offset in comparators. First stage of every comparator is made up of a differential amplifier. As figure (2a) shows Variation in W/L of each transistor causes a deviation of the electrical parameters such as Vth and the other parameters. Therefore the output of differential amplifier would have an offset. This offset limits the resolution of Flash ADCs and causes IDL error. The easiest way to mitigate this issue is to increase W/L.It means decreasing the speed of comparator, and consuming more area and power. Figure 1. Structure of a Flash ADC Figure 2. Illustration of the deviation in CMOS parameters. Another way of decreasing this effect is by averaging in digital domain. In this method, larger number of comparators as would be necessary for the aspired resolution of the flash

2 ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec ADC will be used [1]. The statistical averaging of the comparator results is then performed in the digital domain. This architecture does not reduce the total area of the comparator bench or reduce its power consumption, but that higher sampling speeds can be realized with smaller sized comparators. Figure (2b) shows the effect of this method. The comparator schematic for this method is depicted in figure (3). It consists of a preamplifier, a transconductance amplifier a latch and a memory cell. Figure 3. Structure of the comparator in Flash ADC. Output of the comparator bank is converted into a binary code. By averaging in digital domain, redundant bits will be deleted. Table 1 shows performance of this ADC.[1] Although, this ADC works at high speed, this method is not suitable since it uses a lot of power in its digital part. In this method output of the comparator is no longer determined by its decision alone, but, through the averaging resistors is also influenced by its adjacent comparators. Consequently the input offset of comparators will be reduced by a factor of three. This method has been used in most of the flash ADCs. The main drawback with this method is that we need over-range comparators to maintain the linearity at the edges. V. CAPACITIVE INTERPOLATION Another strategy of reducing the mismatch effect is capacitive interpolation.[5] As figure(5) shows this method uses a capacitive averaging network between the outputs of adjacent amplifiers. Using SC circuits the difference between the input and the threshold level is determined. To achieve high resolution, in the next stage one comparator will be added between every two comparators. And the input of this comparator is determined from the result of the averaging between the two comparators in the last stage. The main advantage of this method is that it doesn t need any extra comparators or any static averaging termination. But still it is complex. Capacitive interpolation combined with distributed front-end sample-and-hold can increase the performance of this method [5]. Table 1. Measured Performance of ADC IV. RESISTIVE AVERAGING Averaging is a well known method to reduce the input offset of the comparators. Resistive averaging uses some resistors between the output of adjacent amplifiers [4]. Figure (4) shows the structure of comparator with resistive averaging. Figure 5. Comparator with capacitive interpolation VI. TIME INTERLEAVING [2] Another way to realize higher sampling rate with respect of low power consumption is to use two identical flash ADC operating in a time interleaved way [6]. Each flash ADC contains several comparators and requires two clock cycles to complete the conversion. Figure (6) shows block diagram of this ADC. Using two converters with three bit resolution, the output would have 6 bit resolution. In the first clock three MSBs of output are determined. During the second clock period input signal will be compared with the new threshold levels to determine the next three bits. Since the clock frequency is twice as input rate, this method is not suitable for at ultra high frequencies. Figure 4. Resistive averaging in the comparator

3 ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec Figure 6. ADC block schematic So every two clocks each comparator provides 6 bits. This structure has the latency of one clock. Switched capacitor and multiplexers are used to perform the function of sample and hold, subtraction and comparison. Table (2) shows the performance of this ADC. Process 0.13 µ m Resolution 6bit Sampling Rate 1GS/s Power supply 1.5 v Power Dissipation 11mW INL <0.5 LSB IDL <1 LSB SFDR@f=200MHZ 38dBc Area mm Table 2. Performance of a time interleaved ADC Figure 8. Block diagram of ADC made up of MCML. Table 3 shows the post-simulation results of MCML Flash ADC. Also the simulation shows that DNLmax and INL max are 0.13-LSB and 0.27-LSB, when standard deviation of input offset is 0.5-LSB. Results show that this method dissipates much power and area. VII. USING MCML CIRCUITS Using MCML circuits can improve performance of Flash ADCs. [7] Figure (7) show the basic structure of a MCML circuit and a MCML latch. The main motivation of using MCML is that its switching speed is independent of the supply voltage as opposed to CMOS circuit. The second motivation is its low dissipation at high frequency ranges. Since MCML dissipate static power, it is independent of operating frequency. Table.3 simulation results for MCML Flash ADC VIII. USING DIFFERENTIAL AMPLIFIER Another way to reduce the input offset of comparator is to use differential amplifier to average the input offset by each of pairs [8]. The structure of the proposed ADC is shown in figure (9). This structure also uses resistor averaging. Figure 7. (a) MCML circuit (b) MCML latch structure Figure (8) shows general block diagram of this ADC. Also MCML circuit is used in comparators and encoders. The resistive ladder provides a reference voltage for 83 preamplifiers where 20 of them are used to provide averaging requirements. 63 MCML comparators are used in the next stage. The output of the comparators are sent to MCML encoders to be converted to binary codes. Figure 9. Architecture of ADC using differential amp. Using differential signaling also has other advantages. It will ensure the immunity of the system to the common mode noise. Since all of the tail currents are reused in each phase, and none of the current sources are turned off. Supply noise due to switching is minimized. Comparator consists of 4 stages. Figure (10) shows the first stage in comparator which

4 ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec is a differential amplifier. The next three stages are latching stages. IX. SIMULATION RESULTS The simulation was done in two parts; in the first part, the goal was to evaluate the effect of W/L variation on the input offset of the comparator. First stage of the comparator in figure (3) with PMOS loads was used in this part. Figure (13) shows the simulation results. Clearly, the higher variations of W/L results the larger input offset Figure 10. Diff pair preamplifier in comparator of ADC Also in this ADC thermometer code is converted to an intermediate gray code using CML gate based logic blocks and in the next stage gray cod is converted to binary code. In this way the effect of bubble errors in the thermometer will be reduced. Figure (11) shows the effect of offset in threshold voltages. Input offset (mv) (W2/L2)/(W1/L1) Figure 13. Input offset due to the variation of W/L In the second part, first part of a 3 bit ADC having 16 comparators was simulated to demonstrate the effect of resistor averaging. The preamplifier in figure (3) was used in the first stage of each comparator. In the next stages, 3 latches added to store the output. Figure (14) shows the structure of the latch.[8] Figure 11. Threshold levels before averaging Figure (12) shows the reduction of the offset after using resistor averaging. Figure 14. Structure of the simulated latch Figure 12. threshold levels after averaging. Table (4) demonstrates the performance summary of this ADC. The simulation results show that this architecture has 4 bit resolution for 5GS/S while consuming low power and area. Eight main comparators and six over range comparators were used. The output of the circuit is a thermometer code, to ensure that the circuit is working properly; a resistive network was used as a testbench to convert the code to analog signal. Figure (15) shows the circuit. Table 4. Performance of ADC using averaging method For ultra high speed applications bipolar transistors are preferred than CMOS [9]. Figure 15. structure of the simulated ADC Figure (16) presents the output of the resistive network when there is no offset in a ramp input of the comparators.

5 ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec comparator. This means more complexity and more power consumption. Figure 16. comparators output in analog domain In the next step input offset was simulated. Figure (17) shows the effect W/L variation in one stage in the output. Figure 17. Output of the comparators having offset To reduce IDL resistor averaging was used [4]. Output of the comparators was connected together by resistors. Figure (18) shows the improvement in IDL of output when this technique is used. Figure 19. Structure of the proposed comparator Since each output bit of ADC has different error probability, another idea is to provide the ASI (ADC State Information) same as CSI (Channel State Information) in OFDM, and send it in parallel of each bit to the soft channel decoder to achieve better BER performance for system. XI. CONCLUSION Different techniques of improving the performance of ADC were discussed. For sampling frequency of 1GS/s interleaving technique is preferred. [5] And for sampling frequencies around of 5 GS/s resistor averaging combined by differential circuits is the best case [8]. For ultra high clock frequencies BJT is a good choice [9]. Resistor averaging improves the resolution but needs more power and area. Capacitor interpolation is better than resistor averaging and increases the resolution but still has complexity and power consumption. MCML circuits dissipate less power and are discussable choice in designing a FLASH ADC. So depend on the application, speed, power consumption and area, different methods could be used. Figure 18. The effect of the resistor averaging X. PROPOSAL Before starting the conversion, by using a reset signal, we can determine the input offset. During the reset time the offset is determined by switched capacitors and will be stored in a memory cell. This offset should be subtracted to the reference voltage to decrease the input offset. Since this idea is complex we can not simulate it. Figure (19) shows the block diagram of the proposed comparator. The main problem with this method is that we need a memory cell, SC and converter for each REFERENCES [1] Christian Paulus, Hans-Martin Bluthgen, Manuel Low, Elisabeth Sicheneder, Nikolaus Briils, Anne Courtois, Marc Tiebout, and Roland Thewes, A 4GS/s 6b Flash ADC in 0.13pm CMOS 2004 Symposium On VLSl Circuits Digest of Technical Papers. [2] [3] David Johns, Ken Martin Analog Integrated Circuit Design [4] Kevin Kattmam, Jeff Barrow, A technique for reducing differential nonlinearity errors in flash A/D converters. IEEE International Solid-State Circuits Conference, Vol. XXXIV, Feb.1991, pp [5] Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner, A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 05) [6] A. RAMANICEAUU, S. SPIRIDON, F. OP T EYNDE. A 6 bit resolution, 1 GSample/S analog to digital converter., Asic Ahead International SRL., Bucharest, Romania [7] H. Dang, M. Sawan, Y. Savaria, Anovel approach for implementing ultra high speed flash ADC using MCML Circuits, IEEE [8] S. Sheikhaei, S. Mirabbasi, and A. Ivanov, A4 _-bit _GS/s flash A/D converter in m CMOS, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2005, pp [9] Jaeisik Lee, Pascal Roux, Ut-Va Koc, Thomas Link, Y ves Baeyens, A 5- b 10-GSample/S A.D Converter for 10-Gb/s Optical Receivers IEEE Journal of solid-state circuits, vol. 39, No.10, October 2004.