CMOS ADC & DAC Principles

Transcription

1 CMOS ADC & DAC Principles Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium Willy Sansen

2 Table of contents Definitions Digital-to-analog converters Resistive Capacitive Current steering Analog-to-digital converters Integrating Successive approximation Algorithmic Flash / Two-step Interpolating / Folding Pipeline Willy Sansen

3 ADC & DAC Output code Analog output (wrt V ref ) 1 Ideal 0.5 Ideal Analog input (with respect to V ref ) 0 Input code Willy Sansen

4 1 DACs Resolution Analog output (wrt V ref ) Ideal V OUT = V REF B IN b 1 b = V REF ( + 2 b + 3 b + N ) N V LSB = V REF 2 N 0 Input code Resolution N b 1 is Most Significant bit (MSB) b N is Least Significant bit (LSB) Willy Sansen

5 The quantisation error of a DAC 1 P Noise = ε 2 dε = /2 - / V ptp = 2 N P Signal = V 2 ptp 8 3 SNR = 2 2N 2 SNR = 6 N db Willy Sansen

6 Static specs : INL & DNL Analog output Analog output Monotonicity Digital input Digital input Differential Nonlinearity : DNL = Y OUT (B) - Y OUT (B-1) - 1 LSB Integral Nonlinearity : INL = Y OUT (B) - Y OUT,id (B) Willy Sansen

7 Dynamic specifications Willy Sansen

8 Spectral content : Spurious free dynamic range db SFDR Frequency (Hz) Willy Sansen

9 Output SNR versus input Signal Limited by distortion -3 db Willy Sansen

10 Table of contents Definitions Digital-to-analog converters Resistive Capacitive Current steering Analog-to-digital converters Integrating Successive approximation Algorithmic Flash / Two-step Interpolating / Folding Pipeline Willy Sansen

11 Resistor string DAC For 10 bit: 1023 resistors and 1024 switches!! Resistive matching! Willy Sansen

12 Binary weighted resistor DAC One Resistor and Switch per bit No guaranteed monotonicity (glitches!) Willy Sansen

13 R-2R DAC I R I R 2 I R 4 I R 8 I R I R 2 I R 4 I R 8 I R I I R + + R I R 8 Smaller area in Resistors! Willy Sansen

14 3-bit charge redistribution DAC Phase Φ1 Better capacitive matching! Willy Sansen

15 4-bit Current steering DAC Resolution limited by Mismatch in the Current sources! Glitches! Willy Sansen

16 The Binary and thermometer codes Monotonicity guaranteed! Willy Sansen

17 Thermometer-code Current steering DAC Willy Sansen

18 Binary, unary, segmented DAC σ ( I) = Binary 2 N σ (I) - 1 LSB I Unary σ (I) I LSB Segmented B LSBs & N-B MSBs 2 B+1 σ (I) - 1 LSB I Van den Bosch,.., Kluwer 2004 Willy Sansen

19 σ(i)/i versus resolution σ (I) I = 1 2 C 2 N C for INL_yield = 90% Yield = 10 % 50 % 90 % 99.7 % Van den Bosch,.., Kluwer 2004 Willy Sansen

20 Switching schemes is centroide! Van den Bosch,.., Kluwer 2004 Miki, JSSC Dec.86, Willy Sansen

21 INL error for different switching schemes Hierarchical symmetrical scheme (type A) Willy Sansen

22 DAC Design: Static Accuracy INL_yield = percentage of functional D/A converters with an INL specification smaller than half an LSB. σ (I) I INL_yield = f (mismatch) = f ( ) WL = 1 4A 2 [ A 2 VT β + ] σ (I) 2 ( ) 2 (V GS -V T ) 2 σ (I) I I 1 2 C 2 N High yield σ (I) small I Large current source area σ (I unit )/I unit = 0.25 % Willy Sansen

23 DAC Design: Calculation W and L W L = I LSB K (V GS -V T ) 2 WL = 1 4A 2 [ A 2 VT β + ] σ (I) 2 ( ) 2 (V GS -V T ) 2 I W = 1.8 µm L = 30 µm σ (I)/I = V GS -V T = 1 V For 0.35 µm CMOS A β 2 %µm A VT 7 mvµm Willy Sansen

24 Floorplan 10-bit segmented DAC M sw M cas M cs Van den Bosch,.., JSSC March 01, Willy Sansen

25 Required output impedance versus resolution Van den Bosch,.., Kluwer 2004 JSSC March 01, bit 1GB/s INL = 99.7 % requires σ(i)/i < 0.5 % : W = 2 µm & L = 8 µm Willy Sansen

26 10-bit 1 GS/s Nyquist Current steering CMOS DAC Current steering DAC 10-bit 1 GS/s 0.35 µm CMOS 110 mw Van den Bosch,.., JSSC, March 01, Willy Sansen

27 SFDR (db) versus relative signal frequency f signal / f clock Willy Sansen

28 FOM (MHz/mW) vs inverse area FOM = 2 N f s (-6dB) P 2 N /area (mm 2 ) Willy Sansen

29 Table of contents Definitions Digital-to-analog converters Resistive Capacitive Current steering Analog-to-digital converters Integrating Successive approximation Algorithmic Flash / Two-step Interpolating / Folding Pipeline Willy Sansen

30 Speed Resolution Limits ADC FOM = 4kT BW DR P 2 N 2BW P Willy Sansen

31 Dual-slope (integrating) ADC Time 1 is constant : T 1 = 2 N T clk V in V x = T 1 R 1 C 1 Time 2 : V x decreases with constant slope : V V x = ref V in T 2 T B out = 2 = T 1 R 1 C 1 V in V V ref ref Johns, Martin, Wiley 1997 Willy Sansen

32 Operation of integrating ADC V in V Time 1 : V x = T ref 1 Time 2 : V R 1 C x = T 2 1 R 1 C 1 T 2 = T 1 V in V ref Willy Sansen

33 Integrating ADC Advantages: High resolution High linearity Low circuit complexity Mainly for voltmeters, Eliminates mains supply 50 Hz if T1 is n x 20 ms Disadvantages: Very slow : Worst case for V in = V ref : 2 2n+1 clock cycli required! Ex. For n = 16 bit (64000) and F clock = 1 MHz : 7.6 s conversion time Mainly for voltmeters, Willy Sansen

34 Successive-approximation ADC Divide interval by 2 ; Determine bit : < 1 : 0 b 1 = MSB < 0.5 : 0 b 2 > 0.25 : 1 b V > : 1 b 4 < : 0 b 5.. Johns, Martin, Wiley 1997 Willy Sansen

35 5-bit Charge redistribution ADC Σ = 2 N C V x 0 1. Sample Mode Accuracy limited by capacitive matching to bit Speed limited by R switch C time constants McCreary, JSSC Dec 75, Johns, Martin, Wiley 1997 Willy Sansen

36 5-bit Charge redistribution ADC V x = -V in 2. Hold mode Bottom plate C to V ref Willy Sansen

37 5-bit Charge redistribution ADC V x = -V in + V ref 2 3. Bit cycling Bottom plate C to V ref if V in > V ref /2 SAR 1 leave C b1 to V ref if V in < V ref /2 SAR 0 leave C b1 to Gnd : try C b2 : try C b2 Willy Sansen

38 Charge redistribution ADC Bottom plate C to V ref Charge redistribution ADC halves V ref in each cycle Algorithmic ADC doubles V error in each cycle Willy Sansen

39 Algorithmic (or cyclic) ADC Advantage : small amount of analog circuitry Difficulty : accuracy x2 Gain amplifier (fully diff. ; C par insensitive) Johns, Martin, Wiley, 2003 Willy Sansen

40 Flash converter 3-bit flash ADC : fastest 2 3 comparators input cap. ~ 2 3 limited to 6 bit (1 2 GS/s) Willy Sansen

41 Evolution in ADC s Uyttenhove, KULeuven, 2003 Willy Sansen

42 Subranging (or two-step) ADC 8-bit two-step ADC : less comparators introduces latency 2 8 = 256 comp. now 32! All circuits : 8b accurate Digital correction required! Johns, Martin, Wiley 1997 Willy Sansen

43 Interpolating saves amplifiers saturating linear near threshold threshold latch saturating Input amplifiers which saturate Van de Grift, JSSC Dec. 87, ; Steyaert CICC 1993 Willy Sansen

44 Interpolating ADC 4-bit interpolating ADC Resistive interpolation leave out 3 out of 4 amps Less power consumption Less input capacitance Johns, Martin, Wiley 1997 Willy Sansen

45 Transfer curves Gain ~ 10 Only the zero crossings carry info Resistors generate the intermediate outputs Resistors average out offsets, etc. Add series resistors to latch inputs to equalize delay times Willy Sansen

46 Averaging with output currents 2 1 I 2a = 3 I I I 2b = 3 I I 2 Interpolating by 3 between output currents I 1 & I 2 Requires 1/3 input amps.: C in /3 Steyaert CICC 93 Willy Sansen

47 Interpolating/Averaging ADC - 1st amp Current mirror interpolator Steyaert CICC 93 Roovers JSSC July 96, Willy Sansen

48 Interpolating : limitations C mirror (ff) f -3dB (MHz) Number of transistors Willy Sansen

49 Folding ADC Analog preprocessing folded signal V in folding circuit fine ADC LSBs coarse ADC MSBs folded signal Folding rate 8 Less comparators Same input capacitance V in Willy Sansen

50 4-bit Folding ADC 4 folding regions V in starts from 0 to 1/4 : from 1/4 to 1/2 : = 4 latches 4-bit flash: 16 comp. folding: 8 comp. Johns, Martin, Wiley 1997 Willy Sansen

51 Folding block realization Folding rate of 4 Differential pairs in parallel! Large C in! Output at higher freq. = f in x folding rate Johns, Martin, Wiley 1997 Willy Sansen

52 Folding + interpolation Folding rate of 4 Interpolate by 2 Lower C in! Van Valburg JSSC Dec. 92, Johns, Martin, Wiley 1997 Willy Sansen

53 Pipelined ADC : n k and single bit per stage Algorithmic conversion in pipeline! n k bit per stage latency of N clock periods Limited to 12 bit by amp. Digital error correction 1 bit per stage Johns, Martin, Wiley 1997 Willy Sansen

54 Pipelined ADC block diagram New sample each clock cycle Johns, Martin, Wiley 1997 Willy Sansen

55 Multiplying DAC DAC + Gain Are merged In one building block: S/H Ni bits ADC Ni bits DAC Multiplying DAC Willy Sansen

56 Multiplying DAC : Phase 1 Vres(i) Cf Cs Vres(i+1) VDAC Φ1 Vres(i) Cf Cs Vres(i+1) Willy Sansen

57 Multiplying DAC : Phase 2 Vres(i) Cf Cs Vres(i+1) VDAC Φ2 Cf VDAC Cs Cs Vres(i+1) = Vres(i) + (Vres(i) - VDAC) Cf G = 1 + Cs Cf = 2 if Cs = Cf Willy Sansen

58 Non-idealities versus Cs 0.25 µm CMOS f s = 400 MHz Uyttenhove, Kuleuven, 2003 Willy Sansen

59 Comparison ADCs Resolution (bits) Clock cycles Per output sample Willy Sansen

60 Impact of device mismatch on resolution/power Two transistors : σ 2 1 (Error) ~ WL σ VT = A VT WL (Accuracy) 2 ~ WL By design : increasing W increases I DS and Power decreasing L increases the speed Speed x (Accuracy) Power = Technol. constant Ref. Kinget,... Analog VLSI.. pp 67, Kluwer Willy Sansen

61 Power and mismatch/noise Accuracy 1/σ 2 (V os ) ~ Area / A VT Dynamic range DR = V srms / (3 σ (V os )) Capacitance C ~ C ox Area Power P = 8 f C V 2 srms Mismatch : P = 24 C ox A VT 2 f DR 2 Noise : P = 8 kt f DR 2 Willy Sansen

62 Noise vs mismatch for DR Mismatch Noise Ref. P.Kinget,... Analog VLSI.. page 67, Kluwer Willy Sansen

63 ADC limitations Ref Walden IEEE Selected Areas Comm. April 1999, ; Uyttenhove 2003 Willy Sansen

64 References D. Johns & K. Martin, Analog Integrated Circuit Design, Wiley 1997 P. Jespers, Integrated Converters, Oxford Univ. Press, 2001 B. Razavi, Principles of Data Conversion System Design, IEEE Press 1995 K. Uyttenhove, High-speed CMOS Analog-to-digital converters, PhD KULeuven, 2003 A. Van den Bosch, High-resolution high-speed CMOS current-steering Digital-to-Analog Converters, Kluwer Ac. Press R. Van de Plassche, Integrated Analog-to-digital and Digital-to-Analog converters, Kluwer Ac. Press, 1994 Willy Sansen

65 Table of contents Definitions Digital-to-analog converters Resistive Capacitive Current steering Analog-to-digital converters Integrating Successive approximation Algorithmic Flash / Two-step Interpolating / Folding Pipeline Willy Sansen