A Novel ROM Architecture for Reducing Bubble and Metastability Errors in High Speed Flash ADCs

Transcription

1 1 A Novel ROM Architecture for Reducing Bubble and Metastability Errors in High Speed Flash ADCs Mustafijur Rahman, Member, IEEE, K. L. Baishnab, F. A. Talukdar, Member, IEEE Dept. of Electronics & Communication Engg., National Institute of Technology Silchar, Silchar, Assam, PIN , India mustafijur@gmail.com, klb@nits.ac.in, fazal@nits.ac.in Abstract In a flash ADC, output of the comparators constitute the thermometer code. This thermometer code is converted to binary code with the help of a thermometer to binary decoder using a ROM. However, this conversion scheme suffers from metastability and bubble errors. A novel ROM architecture has been proposed which suppresses metastability, both first and second order bubble errors. It eliminates the need of an error correction circuit in the front end of the ROM thereby reducing power consumption, area requirement and removing the delay associated with the additional stage. This architecture also eliminates the need of Gray coded ROM and Gray to binary converter thereby making the circuit simpler. Index Terms CMOS memory circuits, analog digital conversion, digital error correction, bubble error, metastability error. I. INTRODUCTION Flash ADCs have high sampling speed, low resolution, large chip area and high power dissipation. They are widely used in systems requiring high data conversion rate like disk drive read channels, high speed Ethernet, wireless communication and RF devices [1]. But with high sampling speed, error correction is crucial to achieve the desired performance. Fig. 1 presents a typical block diagram of flash ADC. The bocks are resistive ladder, comparator block, NAND block, ROM followed by latch. A resistive ladder containing 2 N resistors is used to provide reference voltages to the comparators for an N bit ADC. The input signal is simultaneously compared with each of these reference voltages by the comparator block containing 2 N -1 comparators. The differences between the input signal and reference voltages are applied to the comparator block. The outputs of the comparators constitute what is known as a thermometer code. If input is high with respect to reference level of a particular comparator then the corresponding output of the comparator is high. Under perfect conditions, all comparator outputs below the input level are 1 s, and all comparator outputs above the input level are 0 s. As a result, the thermometer code can easily be converted to a binary code by first using a circuit that Figure 1. Typical block diagram of a flash ADC detects the transition from 1 to 0 and second using the one out of 2 N codes to address a ROM with the binary code. The comparators produce thermometer code i.e. all ones at the bottom and all zeros at the top resembling mercury level in a thermometer. A logic decoder e.g. NAND block detects the 1 to 0 crossing in output of comparator array and addresses a ROM to produce the corresponding digital output. But for fast input signals, small timing differences between response time of comparators combined with unfavorable offset can cause a situation where a one is found above zero. This is called a bubble in the thermometer code or bubble error[2]. As a result along with the decoding block, error correction circuit is also required. On the basis of number of continuous zeros between two ones bubble errors are classified as first order and second order. In this paper, we present a novel ROM which eliminates both first and second order bubble without any decoding block and pre-error correction circuitry. Thermometer code can be directly fed to the ROM to get the error free digital output. Moreover, it also eliminates the need of a Gray coded ROM and Gray to binary converter. The paper is organised as follows: section II discusses the cause of bubble error, section III discusses the existing relevant work for bubble error suppression, section IV presents the proposed ROM and finally the paper is concluded in section V /10/$ IEEE 15

2 2 Figure 4. Two input NAND gate for decoding 1 to 0 transition. Figure 2. Cause of bubble errors. TABLE I TWO INPUT NAND BLOCK OUTPUT FOR CORRECT AND ERRONEOUS CODES Figure 3. Diagram showing routing of clocks from LSB comparator COMP 1 to higher comparators. A is correct code expected A is A s two input NAND output. B is B s two input NAND output. C is C s two input NAND output. II. BUBBLE ERROR In Fig. 2 bold line shows the actual reference voltage while dashed line shows shifted reference due to offset. Vertical lines corresponding to t 1, t 2, t 3, t 4 represent the time instants of comparison of comparators COMP1, COMP2, COMP3, COMP4 respectively and hence reflect the delay in the response time of the comparators. This delay is due to difference in comparator response time and clock skew. Clock skew occurs due to long clock routing from LSB comparator to MSB comparator. The clock signal does not reach the comparators simultaneously i.e. reaches the higher comparators late and hence causes delay. As shown in Fig. 3 clock signal will reach LSB comparator COMP1 earlier than higher comparator COMP4. The oblique line in Fig. 2 is the fast varying input signal. The bits in circle are the expected correct bits in ideal case which will result if all comparators compare at the same instant say t 1 and if there is no shifting in reference voltages. The bits in square are the erroneous bits due to shifted reference and timing differences in the response time of the comparators. Fig. 2(a) and Fig. 2(b) respectively shows the case of first and second order bubble. As shown in Fig. 2(a), let us consider the comparison at time instant t 1. In /10/$ IEEE 16 ideal case, expected code at t 1 will be 001 since all the comparators are expected ideally to respond at the same instant t 1 using the bold reference levels. However, clock arrives at COMP3 at time instant t 3 i.e. after a delay of 2 where is the clock skew between adjacent comparators. In the mean time the fast signal increases and exceeds the shifted reference level corresponding to comparator COMP3. As a result COMP3 outputs a wrong 1 and the code becomes 101 instead of 001. Similarly the case of second order bubble can be seen in Fig. 2(b). It can be seen in Fig. 2 that the probability of second order bubble is less compared to first order bubble and requires larger timing mismatch [3]. The simplest circuit that can detect a 1 to 0 transition is a two-input NAND gate (with the input from the top comparator complemented) as shown in Fig. 4. In Table-I, column A shows the thermometer code generated by the comparators. The 1 to 0 transition point rise and fall for different input range and this point is decoded and used to address an ordinary binary ROM [2]. As explained earlier in case of high frequency input signal, small timing difference between the response time of the adjacent

3 3 Figure 5. Three input NAND gate capable of decoding 1 to 0 transition and removing first order bubble. TABLE II THREE INPUT NAND BLOCK OUTPUT FOR CORRECT AND ERRONEOUS CODES Figure 6. Schematic of an ordinary binary ROM. A is correct code expected A is A s three input NAND output. B is B s three input NAND output. C is C s three input NAND output. comparators and unfavorable reference variations due to offsets can cause bubble in thermometer code. However, in the presence of a first order bubble as shown in column B, there are two 1 to 0 transitions and consequently with two input NAND two ROM lines are addressed as show in column B of Table I. The output code can then be completely wrong. The output code is then the AND function of all the ROM lines which are addressed by the comparators. Even a small error can cause a large glitch in the output code. III. EXISTING WORKS Many techniques are available to address first order bubble problem such as voting process, Wallace tree adder, 3 input NAND gate etc. Voting process is used to eliminate the first order bubble [4]. In this method, the state of a particular output is qualified by voting by the neighbors. This technique requires additional amount of digital circuitry which increases the power. The Wallace tree adder technique is effective in removing the first as well as second order bubbles but comes at the cost of speed reduction and increased power dissipation [3]. In three input NAND gate technique one 1 followed by two 0 s will be qualified as 1 and this addresses the respective ROM line [3]. This technique effectively removes the first Figure 7. Schematic of proposed ROM. Transistors M1, M2 and M3 form the circuit for ROM line L=5. order bubble but cannot address second and higher order bubbles. When erroneous thermometer codes are fed to three input NAND gates, then the corresponding output generated are shown in column A, B and C of Table II. For second order bubble case, there are two 1 to 0 transition and hence two ROM lines are addressed at a time causing a large glitch in output code. For example if two erroneous 1 s from the three input NAND gate with decimal weight 10 (1010) and 13 (1101) addresses a 16 by 4 binary NAND ROM then binary output will be 8 (1000), which is a large deviation relative to 13 and 10. It is reported that Gray encoded ROM can reduce bubble errors [5]. When two ROM lines are selected, the output is an AND function of two selected code. Two selected ROM lines are adjacent and since there is only one bit change in the adjacent code of a Gray coded ROM, the error is small. The major disadvantage of using Gray code ROM is the requirement of an additional Gray to binary code conversion block. This conversion is slow and can affect the performance of high speed ADCs. Finally, three input NAND scheme with some modifications in ordinary binary ROM enable removal of both first order and second order bubble as in [6]. However, /10/$ IEEE 17

4 4 TABLE III OUTPUT OF PROPOSED CIRCUIT FOR CORRECT AND ERRONEOUS CODES A is correct thermometer code as expected A shows proposed ROM s line selection for code A B shows proposed ROM s line selection for code B C shows proposed ROM s line selection for code C 1 in column A,B and C indicate ROM line selection which occurs when M1, M2 and M3 turns on and pulls down node X in Fig. 7. in our scheme we have eliminated the three input NAND block completely and only used our proposed ROM so as to remove both first order and second order bubble. IV. PROPOSED ROM In three input NAND scheme, the NAND gates perform the function of decoding and correcting first order bubble and finally selects a binary/gray ROM line. In our scheme we have removed the NAND gates and modified a binary ROM by adding three additional transistors per selection line in such a way that both first and second order bubbles are removed. As a result, no additional decoding and error correction block is required in the front end of proposed ROM. Since second order bubble has been removed Gray coded ROM and Gray to Binary converter is also not needed. The circuit formed by the three transistors is shown in Fig. 7. An ordinary Binary ROM is shown in Fig. 6. In ordinary binary ROM, when a selection line L is high the connected transistors are turned on and corresponding output lines are pulled down. As shown in Fig. 7, in proposed ROM the gates of the transistors MB3 and MB0 are biased with voltage V DD. Their sources are sorted and connected to node X whose state is controlled by transistors M1, M2, M3. Thus line L will be selected when MB3 and MB0 are on and this will happen when their sources are at low voltage i.e. node X is pulled down. For this to occur transistors M1, M2, M3 in the circuit for line L should be on. The inputs to the circuit at a particular selection line come from the corresponding level L, the next higher level L+1, the second higher level L+2 and second lower level L-2. All the transistors will turn on if a low voltage is applied to the gate of PMOS M1 and source of NMOS M3 and a high voltage is applied Figure 8. Block diagram of flash ADC after using proposed ROM. to the gates of NMOS M2 and M3. Thus the circuit at the ROM line L searches for the pattern [1,X,1,0,0] at the ROM lines [L-2, L-1, L, L+1, L+2] respectively where X is don t care. The circuit does not check the state of the immediate lower level. Removal of bubble errors and metastability is explained below. A. First order Bubble In Table III column B shows thermometer code having first order bubble and column B shows ROM line selection (indicated by 1 ) of proposed ROM. In column B there are two 1 to 0 transitions at the lines 2 and 4. The circuit at the line L=2 receives [1,X,1,0,1] as input at ROM lines [L-2,L- 1,L,L+1,L+2] i.e. at [0,1,2,3,4 ] and is turned off. Thus the line L=2 is not selected. The circuit at the line L=5 receives [1,X,1,0,0] as input at ROM lines [L-2,L-1,L,L+1,L+2] i.e. at [2,3,4,5,6]. This is the desired search pattern and consequently circuit at L=4 is turned on. Thus line L=4 is selected. The bubble has been removed and upper 1 to 0 transition has been considered correct. The upper transition is more closer to actual result because both offset and comparator delay are responsible for first order bubble. B. Second order Bubble In Table III column C shows thermometer code having second order bubble and column C shows ROM line selection (indicated by 1 ) of proposed ROM. In column C there are two 1 to 0 transitions at the lines 2 and 5. The circuit at the line L=2 receives [1,X,1,0,0] as input at ROM lines [L-2,L-1,L,L+1,L+2] i.e. at [0,1,2,3,4 ]. This is the desired search pattern and consequently circuit at L=2 is turned on. Thus the line L=2 is selected. The circuit at the line L=5 receives [1,X,1,0,1] as input at ROM lines [L-2,L-1,L,L+1,L+2] i.e. at [3,4,5,6,7] and is turned off and hence line L=5 is not selected. The bubble has been removed and lower 1 to 0 transition has been considered correct /10/$ IEEE 18

5 5 The lower transition is more closer to actual result because comparator delay is mainly responsible for second order bubble [7]. Since clock routing has been done from LSB to MSB, the lower one is correct. C. Metastability If the input signal and reference level are very close to each other then the comparator may be unable to resolve the difference. Consequently, comparator produces metastable output voltage (V meta ) whose magnitude lies between logic 1 and logic 0. This situation is called metastability and is a main cause of errors in ADC. The problem of metastability can be solved by properly sizing the transistors M1, M2, M3 in Fig. 7 so that V meta is always interpreted as high. Oxford University Press, New York, [9] Sunghyun Par, Yorgos Palaskas, and Michael P. Flynn, A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS IEEE Journal of Solid-State Circuits, Vol. 42, no. 9, pp , Sept [10] K. Sushihara, H. Kimura, Y. Okamoto, K. Nishinura and A. Matsuzawa, A 6b 800MS/s CMOS ADC, IEEE ISSCC Dig. Tech. Papers, pp ,Feb The voltage levels at the output lines of the proposed ROM are deviated from proper logic levels due to presence of additional transistors as shown in Fig. 7. Therefore, the threshold of the latches at the output section are set accordingly so as to restore proper logic levels. Fig. 8 shows the block diagram of flash ADC after using proposed ROM. It no longer contains the NAND block as shown in Fig. 1. CONCLUSION In this paper a novel ROM architecture has been proposed for reducing bubble errors and metastability. The proposed ROM removes both first and second order bubble without any error correction circuit in the front end. It also eliminates the need of Gray coded ROM along with Gray to binary encoder. This method enables us to use simple binary coded ROM with just three additional transistors per line. Due to reduction in circuitry there is less power dissipation and less area requirement. Moreover, delay associated with the additional NAND stage is completely removed. REFERENCE [1] Choi, M. and Abidi, A.A., A 6-b 1.3-Gsample/s A/D Converter in um CMOS, IEEE Journal of Solid-State Circuits, vol.36, pp ,December [2] Scholtens, P. C. S and Vertregt M., A 6-b 1.6-Gsample/s flash ADC in 0.18um CMOS using averaging termination, IEEE Journal of Solidstate Circuits, vol. 37, no.7, pp , Dec [3] Koen Uyttenhove and Michiel Steyaert S. J., A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25um CMOS, IEEE Journal of Solid-state Circuits, vol. 38, no. 7, pp , July [4] Christopher W. Mangelsdorf, A 400-MHz Input Flash Converter with Error Correction, IEEE Journal of Solid-state Circuits, vol. 25, no. 1, pp , February [5] Clemenz L. Portmann, Member IEEE, and Teresa H. Y. Meng, Powerefficient metastability error reduction in CMOS flash A/D converters, IEEE Journal of Solid-state Circuits, vol. 31, no.8, pp , August [6] Niket Agrawal and Roy Paily, An Improved ROM architecture for Bubble Error Suppression in High Speed Flash ADCs, in Proc. Of Annual IEEE Student Paper Conference (AISPC'08), Denmark, 2008, pp.1-5. [7] Padoan. S, Boni. A, Moraridi. C and Venturi. F, A novel coding scheme for the ROM of parallel ADCs, featuring reduced conversion noise in the case of single bubbles in the thermometer code, in IEEE ICECS, 1998, pp [8] Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design, /10/$ IEEE 19