Assoc. Prof. Dr. Burak Kelleci

Transcription

1 DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING ANALOG-TO-DIGITAL AND DIGITAL- TO-ANALOG CONVERTERS Assoc. Prof. Dr. Burak Kelleci Fall 2018

2 OUTLINE Nyquist-Rate DAC Thermometer-Code Converter Hybrid Converter Ramp Converter ADC and DAC - Week 4 2

3 Thermometer-Code Converter Another method is to recode the digital input value to a thermometer code. Thermometer code has 2 N -1 digital inputs to represent 2 N different digital values. Decimal Binary Thermometer Code b 1 b 2 b 3 d 1 d 2 d 3 d 4 d 5 d 6 d ADC and DAC - Week 4 3

4 Thermometer-Code Converter Thermometer code based converters circuit complexity is higher than binary code based converter. It has advantages over its binary counterpart Low DNL errors Guaranteed monotonicity Reduced glitching noise. These advantages makes thermometer based converters attractive for small number of bits. ADC and DAC - Week 4 4

5 Resistor based thermometer-coded converter R F d 1 d 2 d 3 d 4 d 5 d 6 d 7 V out R R R R R R R -V ref If resistor areas are larger than switch areas, the size of resistor based thermometer coded DAC is not increased compared to binary-weighted DAC. To built R, 2R and 4R, 7R resistors are needed. ADC and DAC - Week 4 5

6 Current mode thermometer-coded converter Resistors are not scaled well with advanced process technologies as MOSFET. A current mode approach yields better area shrinkage compared to resistor based approach. d i M2 I out M3 d i M1 generates the current that will be routed to the output Depending on the digital inputs, current generated by M1 flows through M2 or M3 V bias M1 Not turning off M1 totally, improves the switching timing. ADC and DAC - Week 4 6

7 Current mode thermometer-coded converter Bias voltage required by M1 is usually generated by a diode connected transistor. Matching of currents on M1 and diode connected transistor depends on distance between them, process matching performance and matching of VDS and VGS of transistors. Since gate current of MOSFET is zero, their gate-source voltage will be the same. The zero gate current assumption is not valid for advanced technologies where gate leakage current is significant. ADC and DAC - Week 4 7

8 Current mode thermometer-coded converter Mismatch on drain-source voltages will generate current mismatch due to the channel length modulation. To minimize this effect, a cascode structure is usually used. Mismatch due to the process still limits the performance. To obtain well matched current sources dynamic techniques with current switching is used. With this technique up to 16-bit accuracy is obtained for audio frequency DAC. ADC and DAC - Week 4 8

9 Current mode thermometer-coded converter R F d 1 d 2 d 3 d 4 d 5 d 6 d 7 V out I I I I I I I R F Iref d 1 d 2 d 3 d 4 d 5 d 6 d 7 V out VDD/2 ADC and DAC - Week 4 9

10 Instead of using and amplifier, current sources drive directly the load I I I I I I I d 1 d 2 d 3 d 4 d 5 d 6 d 7 V OUT R L ADC and DAC - Week 4 10

11 Practical current sources have finite output impedance. Moreover, switches have also finite on resistance. I R OUT R ON d N R EQ /B B I EQ R L R = R + EQ OUT R ON R L ADC and DAC - Week 4 11

12 The equivalent output current is I ROUT + VDD I EQ = R + R OUT Assuming k is the number of cells that are switched on, output voltage becomes V OUT = k I EQ R R L L R + This equation indicates that there is gain error and nonlinearity in terms of INL R EQ EQ / k / k = ON I EQ R L k 1+ k = R R L EQ ADC and DAC - Week 4 12

13 INL is in LSBs INL ( ) ( n k ) n k = k k = 0,, k The maximum of INL occurs at the mid-code and approximately equals to n INL = 2 2 MAX In order to obtain less than 1LSB INL error, equivalent output resistance must be greater than R EQ R L n 2 2 ADC and DAC - Week 4 13

14 For example, to get 12-bit performance for 25Ohm load resistance, equivalent resistance must be greater 100MegaOhm. In modern CMOS processes this level of output resistance can be achieved using cascode structures. ADC and DAC - Week 4 14

15 Mismatch between current sources limits the performance. To obtain 99.9% yield, current mismatch must I n / I For example, to obtain 12-bit performance mismatch must be lower than 0.5%. This level is not possible unless special processing steps or digital signal processing techniques are used. Note that, 5% mismatch will results in 5-bit resolution. ADC and DAC - Week 4 15

16 Dynamically matched current source In this method, a current source is first calibrated by connecting it to a reference current. Opening S1 switch the gate source voltage remains constant since there is no current flow through MOSFET gate. Calibration Phase Iref I out S 2 Current Source Mode Iref I out S 2 S 1 M1 S 1 M1 C GS C GS ADC and DAC - Week 4 16

17 Hybrid Converters (Segmented Converters) Combining binary approach with thermometer technique yields to Hybrid converters. Top few MSBs are realized using thermometer coded approach and binary approach is used for lower LSBs. Since LSBs require less accuracy and have less glitch energy, area saving is performed by using binary approach for LSBs. b 3 b 2 b 1 Binary-to-Thermometer Decoder R F d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 b 4 b 5 b 6 V out I I I I I I I I/2 I/4 I/8 ADC and DAC - Week 4 17

18 RAMP CONVERTER At the beginning of conversion reset switch discharges the capacitance C. Then the counter starts to count from zero. Comparator closes the switch till count number reaches the input level. 2 N clock cycles are required to reach Full Scale. V OUT = k C I f S Input Reset Comp I C S&H Clk/2 n V out k is the digital code Count Clk ADC and DAC - Week 4 18

19 RAMP CONVERTER Ramp converter requires 2 N clock cycles to reach Full Scale. If two current sources are used to charge the number of clock cycles are reduced. Reset S&H V out Input MSB-M Comp I M Input REST Comp I C Clk/2 n-m Count Count Clk Clk ADC and DAC - Week 4 19

20 DUTY-CYCLE CONVERTER The duty-cycle converter converts input signal into series of pulses. Counter connects low-pass filter input to Vref is counter value is less than input value, otherwise to zero. Filter removes high frequency content. 2 N clock period is required for conversion. Vref Filter V out Input Comp Count Clk ADC and DAC - Week 4 20