10-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23

Transcription

1 19-195; Rev 1; 1/4 1-Bit, Low-Power, Rail-to-Rail General Description The is a small footprint, low-power, 1-bit digital-to-analog converter (DAC) that operates from a single +.7V to +5.5V supply. The on-chip precision output amplifier provides rail-to-rail output swing. Drawing an 85µA supply current at 3V, the is ideally suited to portable battery-operated equipment. The utilizes a 3-wire serial interface compatible with SPI /QSPI /MICROWIRE and DSP-interface standards. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers to allow direct interfacing to optocouplers. The incorporates a poweron reset (POR) circuit that ensures that the DAC begins in a zero-volt-state upon power-up. A power-down mode that reduces current consumption to.3µa may be initiated through a software command. The is available in a small 6-pin SOT3 package. For dual and quad 1-bit versions, see the MAX571 and MAX5741 data sheets. For single, dual, and quad 1-bit versions, see the MAX571, MAX57, and MAX574 data sheets. The is specified over the automotive temperature range of -4 C to +15 C. Automatic Tuning Gain and Offset Adjustment Power Amplifier Control Process Control I/O Boards Battery-Powered Equipment VCO Control Applications Features Wide -4 C to +15 C Operating Temperature Range Low 85µA Supply Current Ultra Low.3µA Power-Down Supply Current Single +.7V to +5.5V Supply Voltage Fast MHz 3-Wire SPI/QSPI/MICROWIRE and DSP-Compatible Serial Interface Schmitt-Triggered Inputs for Direct Interfacing to Optocouplers Rail-to-Rail Output Buffer Power-On Reset to Zero Volts Three Software-Selectable Power-Down Output Impedances (1kΩ, 1kΩ, Hi-Z) Tiny 6-Pin SOT3 Package PART Ordering Information TEMP RANGE PIN- PACKAGE TOP MARK EUT-T -4 C to +85 C 6 SOT3-6 ABCP AUT-T -4 C to +15 C 6 SOT3-6 AAUC SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. Functional Diagram Pin Configuration V DD GND TOP VIEW DAC REGISTER REF+ REF- 1-BIT DAC OUTPUT BUFFER OUT V DD 1 6 OUT INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC 1kΩ 1kΩ GND 5 CS CS SCLK DIN POWER-ON RESET DIN 3 4 SOT3 SCLK Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 1-Bit, Low-Power, Rail-to-Rail ABSOLUTE MAXIMUM RATINGS V DD to GND...-.3V to +6V OUT, SCLK, DIN, CS to GND...-.3V to (V DD +.3V) Maximum Current into Any Pin...±5mA Continuous Power Dissipation (T A = +7 C) 6-Pin SOT3 (derate 9.1mW/ C above +7 C)...77mW Operating Temperature Range EUT...-4 C to +85 C AUT...-4 C to +15 C Maximum Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = +.7V to +5.5V, GND =,, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at, T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (NOTE 1) Resolution N 1 Bits Integral Nonlinearity Error INL (Note ) ±.5 ±4 LSB Differential Nonlinearity Error DNL Guaranteed monotonic (Note ) ±1 LSB Zero-Code Error OE Code = % of FS Zero-Code Error Tempco.3 ppm/ C Gain Error GE Code = 3FF hex -3 % of FS Gain Error Tempco.6 ppm/ C DAC OUTPUT Output Voltage Range No load (Note 3) V DD V DC Output Impedance Code = hex.8 Ω Short-Circuit Current Wake-Up Time Output Leakage Current P ow er - d ow n m od e = outp ut hi g h i m p ed ance ±18 na DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage V IH, +5V.7 x V DD V Input Low Voltage V IL, +5V.3 x V DD V Input Leakage Current I IN Digital inputs = or V DD ±.1 ±1 µa Input Capacitance C IN 5 pf ma µs

3 1-Bit, Low-Power, Rail-to-Rail ELECTRICAL CHARACTERISTICS (continued) (V DD = +.7V to +5.5V, GND =,, C L = pf, T A = T MIN to T MAX, T A = +5 C, unless otherwise noted. Typical values are at, T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR.5 V/µs Voltage Output Settling Time 1 hex to 3 hex (Note 4) 4 1 µs Digital Feedthrough Any digital inputs from or V DD. nv-s Digital-Analog Glitch Impulse POWER REQUIREMENTS Major carry transition (code 1FF hex to code hex) 1 nv-s Supply Voltage Range V DD V All digital inputs at or V DD, V DD = 3.6V Supply Current with No Load I DD All digital inputs at or V DD, V DD = 5.5V µa Note 1: DC specifications are tested without output loads. Note : Linearity guaranteed from code 9 to code 995. Note 3: Offset and gain error limit the FSR. Note 4: Guaranteed by design. INL (LSB) Power-Down Supply Current I DDPD All digital inputs at or V DD, V DD = 5.5V.9 1 µa TIMING CHARACTERISTICS (FIGURE ) (Timing is tested with no load) SCLK Clock Frequency f SCLK MHz SCLK Pulse Width High t CH ns SCLK Pulse Width Low t CL ns CS Fall to SCLK Rise Setup t CSS 15 ns DIN Setup Time t DS 15 ns DIN Hold Time t DH ns SCLK Falling Edge to CS Rising Edge INTEGRAL NONLINEARITY vs. (T A = +5 C) t CSH 1 ns CS Pulse Width High t CSW 8 ns (T A = +5 C, unless otherwise noted.) toc1 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. (T A = +5 C) OR +5V Typical Operating Characteristics 3 toc TOTAL UNADJUSTED ERROR (%) TOTAL UNADJUSTED ERROR vs. (T A = +5 C) toc3

4 1-Bit, Low-Power, Rail-to-Rail (T A = +5 C, unless otherwise noted.) INL (LSB) INTEGRAL NONLINEARITY vs. (T A = +15 C) toc4 DNL (LSB) Typical Operating Characteristics (continued) DIFFERENTIAL NONLINEARITY vs. (T A = +15 C) OR +5V toc5 TOTAL UNADJUSTED ERROR (%) TOTAL UNADJUSTED ERROR vs. (T A = +15 C) toc6 INL (LSB) INTEGRAL NONLINEARITY vs. (T A = -4 C) toc7 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. (T A = -4 C) OR +5V toc8 TOTAL UNADJUSTED ERROR (%) TOTAL UNADJUSTED ERROR vs. (T A = -4 C) toc INL AND DNL (LSB) WORST-CASE INL AND DNL vs. TEMPERATURE MAXIMUM INL MINIMUM INL MINIMUM DNL MAXIMUM DNL TEMPERATURE ( C) toc1 VOUT (V) SOURCE AND SINK CURRENT CAPABILITY () = 3FF HEX, SOURCING CURRENT FROM OUT = 3 HEX, SOURCING CURRENT FROM OUT = 1 HEX, SINKING CURRENT INTO OUT =, SINKING CURRENT INTO OUT I SOURCE/SINK (ma) toc11 VOUT (V) SOURCE AND SINK CURRENT CAPABILTIY () = 3FF HEX, SOURCING CURRENT FROM OUT = 3 HEX, SOURCING CURRENT FROM OUT = 1 HEX, SINKING CURRENT INTO OUT =, SINKING CURRENT INTO OUT I SOURCE/SINK (ma) toc1 4

5 1-Bit, Low-Power, Rail-to-Rail (T A = +5 C, unless otherwise noted.) SUPPLY CURRENT (µa) SUPPLY CURRENT vs. SUPPLY VOLTAGE = 3FF HEX = toc13 POWER-DOWN SUPPLY CURRENT (na) Typical Operating Characteristics (continued) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE toc14 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. CS INPUT VOLTAGE toc SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) CS INPUT VOLTAGE (V) FULL-SCALE SETTLING TIME () toc16 FULL-SCALE SETTLING TIME () toc17 HALF-SCALE SETTLING TIME () toc18 1µs/div TO 3FF HEX C L = pf 3FF HEX TO C L = pf µs/div 1 HEX TO 3 HEX C L = pf 1µs/div HALF-SCALE SETTLING TIME () toc19 EXITING POWER-DOWN () toc DIGITAL-TO-ANALOG GLITCH IMPULSE () toc1 HEX 1mV/div 3 HEX TO 1 HEX C L = pf C L = pf HEX TO 1FF HEX C L = pf 1µs/div 5µs/div 5ns/div 5

6 1-Bit, Low-Power, Rail-to-Rail (T A = +5 C, unless otherwise noted.) DIGITAL-TO-ANALOG GLITCH IMPULSE () toc Typical Operating Characteristics (continued) CLOCK FEEDTHROUGH () toc3 V/div 1mV/div 1FF HEX TO HEX C L = pf C L = pf 1mV/div 5ns/div 5ns/div Pin Description PIN NAME FUNCTION 1 V DD Power-Supply Input GND Ground 3 DIN Serial Data Input 4 SCLK Serial Clock Input 5 CS Active-Low Chip-Select Input 6 OUT DAC Output Voltage 6

7 1-Bit, Low-Power, Rail-to-Rail Detailed Description The voltage-output, 1-bit DAC, offers a full 1-bit performance in a small 6-pin SOT3 package. The SOT3 footprint is less than 9mm. The has less than 1LSB differential nonlinearity error, ensuring monotonic performance. The device uses a simple 3-wire, SPI/QSPI/MICROWIRE and DSP-compatible serial interface that operates up to MHz. The incorporates three shutdown modes, making it ideal for low-power applications. Analog Section The consists of a resistor string, an output buffer, and a POR circuit. Monotonic digital-to-analog conversion is achieved using a resistor string architecture. Since VDD is the reference for the, the accuracy of the DAC depends on the accuracy of VDD. The low bias current of the allows its power to be supplied by a voltage reference such as the MAX63. The 1-bit DAC code is binary-unipolar with 1LSB = VDD/14. Output Buffer The DAC output buffer has a rail-to-rail output and is capable of driving a 5kΩ resistive load in parallel with a pf capacitive load. With a capacitive load of pf, the output buffer slews.5v/µs. With a 1/4FS to 3/4FS output transition, the amplifier output settles to 1/LSB in less than 1µs when loaded with 5kΩ in parallel with pf. The buffer amplifier is stable with any combination of resistive loads greater than 5kΩ and capacitive loads less than pf. Program the input register bits to power-down the device. The DAC registers are preserved during powerdown and upon wake-up, the DAC output is restored to its pre-power-down voltage. Power-On Reset The has a POR circuit to set the DACs output to zero when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system startup, such as after a loss of power. Upon initial power-up, an internal power-on reset circuit ensures that all DAC registers are cleared, the DAC is powered-down, and its output is terminated to GND by a 1kΩ resistor. An 8µs recovery time after issuing a wake-up command is needed before writing to the DAC registers. Digital Section 3-Wire Serial Interface The digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP interfaces. The chip-select input (CS) frames the serial data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and latched into the input register on the falling edge of the serial clock input (SCLK). After 16 bits have been loaded into the serial input register, the serial input register transfers its contents to the DAC latch. CS may then either be held low or brought high. CS must be brought high for a minimum of 8ns before the next write sequence, since a write sequence is initiated on a t CH SCLK t CL t CSS t CSW t DH t CSH CS t DS DIN C3 SO Figure 1. Timing Diagram 7

8 1-Bit, Low-Power, Rail-to-Rail Table 1. Serial Interface Mapping 16-BIT SERIAL WORD MSB LSB MODE OUTPUT C3 C C1 C D9 D8 D7 D6 D5 D4 D3 D D1 D S1 S 1-Bit DAC Code Set and Update DAC X X X X X X X X X X Wake-Up = V DD x /14 Current DAC setting (initially ) X X X X X X X X X X 1 Power-Down Floating X X X X X X X X X X 1 Power-Down 1kΩ to GND X X X X X X X X X X 1 1 Power-Down 1kΩ to GND X = Don t Care falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. Figure 1 shows the complete 3-wire serial interface transmission. Table 1 lists serial-interface mapping. The first command after VDD is applied must be the wakeup command. Power-Down Modes The includes three software-controlled power-down modes that reduce the supply current to below 1µA. In two of the three power-down modes, OUT is connected to GND through a resistor. Table 1 lists the three power-down modes of operation. When in power-down, the does not respond to the set and update command. Applications Information Device Powered by an External Reference The generates an output voltage proportional to V DD, coupling power-supply noise to the output. The circuit in Figure rejects this power-supply noise by powering the device directly with a precision voltage reference, improving overall system accuracy. The MAX63 (+3V, 75ppm) or the MAX65 (+5V, 75ppm) precision voltage references are ideal choices due to the low-power requirements of the. This solution is also useful when the required full-scale output voltage is less than the available supply voltages. Digital Inputs and Interface Logic The 3-wire digital interface for the is compatible with SPI, QSPI, MICROWIRE, and DSP. The three digital inputs (CS, DIN, and SCLK) load the digital input serially into the DAC. All of the digital inputs include IN MAX65 MAX63 Schmitt-trigger buffers to accept slow-transition interfaces. This allows optocouplers to interface directly to the without additional external logic. The digital inputs are compatible with CMOS-logic levels. Power-Supply Bypassing and Layout Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the supply ground is short and low impedance. Bypass V DD with a.1µf capacitor to ground as close as possible to the device. Chip Information TRANSISTOR COUNT: 3856 PROCESS: BiCMOS OUT GND Figure. Powered By Reference V DD GND OUT 8

9 1-Bit, Low-Power, Rail-to-Rail Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 6LSOT.EPS PACKAGE OUTLINE, SOT-3, 6L 1-58 F 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.