Asynchronous SAR ADC: Past, Present and Beyond. Mike Shuo-Wei Chen University of Southern California MWSCAS 2014
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1 Asynchronous SAR ADC: Past, Present and Beyond Mike Shuo-Wei Chen University of Southern California MWSCAS
2 Roles of ADCs Responsibility of ADC is increasing more BW, more dynamic range Potentially simplify analog pre-conditioning circuits Reconfigurable system imposes more weights on ADC IF Sampling, except IF is becoming RF Direct RF Sampling spec/cost of ADC? 2
3 Who is driving higher speed? Low Medium resolution (6bit) with GS/s High speed optical links, instrumentations. High Medium resolution (10bit), with 100MS/s to a few GS/s. Radars, Commercial Communications, or wideband radios, such as 60GHz, UWB, SDR, Cognitive radio. Power efficiency is a key issue! 3
4 Why possible now? Cost of such ADCs used to be intimidating, bounded by Walden wall. CMOS technology provides tremendous opportunity. Circuit designers enjoy inventing and polishing ADC architectures. Given the resolution, speed and power efficiency advanced by orders of magnitude over the past decade 4
5 Walden s ADC Survey Robert Walden, Analog-to-Digital Converter Survey and Analysis, Journal of selected area in communications,
6 Optimal ADC Architecture? Architecture that promotes mostly digital operation so it scales with CMOS technology No high precision analog requirement Tolerate low voltage design Take advantage of device speed 6
7 ADC Architecture Overview Flash Pipeline SAR Vref Vin Vin Stage 1 Stage N Decoder S/H ADC Stage i DAC + DAC Decoder CLK CLK Complexity Conv. time 7
8 Successive Approximation (SAR) Algorithm Binary searching. N-bit resolution requires N comparisons, i.e. 1 bit per cycle. 8
9 Typical SAR Logic N-bit SAR requires at least N+1 cycles. Typically, a fast clock is used to divide the time into S/H, and N bit comparison. DAC and SAR logic change reference levels. 9
10 DAC Implementation Capacitor array to perform sampling and charge redistribution fast and low power. This is most commonly used. However, other DAC implementations are possible, such as resistor ladder network or capacitor-resistor hybrid version. 10
11 Sampling Phase Sampling on the capacitive DAC. 11
12 First MSB comparison All capacitors are connected to Vcm. 12
13 Second MSB Comparison If Vin > 0 The rest of bit conversions follows. 13
14 Why SAR? 1. Mostly digital components good for technology scaling 2. No linear, high precision amplification is required fast, low power 3. Minimal hardware 1 comparator is needed 14
15 Evolving Ecosystem 15
16 SAR ADC in the past 10 years 16
17 Limitation of Synchronous SAR MSB MSB-1 MSB-2 LSB Internal CLK Tracking Phase Cost Jitter No redundant comparison High-speed internal clock Speed limitation Synchronous Conversion Phase Worst-case cycle time Margin for clock jitter Sampling Instants 17
18 Asynchronous SAR ADC Concept MSB MSB-1 MSB-2 LSB Tracking Phase Asynchronous Conversion Phase Sampling Instants Vref Vin '1' 1 2 '0' Vref 3 4 '1' Vref 5 8 Vref Full Scale t cmp t cmp C g m V ln( V FS ID ) Gnd Conversion Time M. S.W. Chen, R. Brodersen, A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS, ISSCC 06. V ID 18 Still uniform sampling
19 How much time can it save? Conv. time between sync. and async. SAR, assuming regenerative comparator is used. It varies with residue voltage profile Best case Worst case 19
20 Best Case Peak input value yields larger Vres pattern 20
21 Worst Case (I) Input with alternative polarity smaller magnitude 21
22 Worst Case (II) As N increases, it approaches ½, same as the best case! Note that: Since there is no synchronous clock uncertainty, more saving is possible! Actual time saving depends on input signal characteristics. 22
23 First Asynchronous SAR ADC Prototype Vin Vref+ Vref- Non-Binary Capacitor Network SR Latch Clk0 Clk1 2-phase clock generation Pulse Generator Ready Generator Sequencer (Multi-Phase CLK) iclk0 iclk6 Switch Logic & Bit Caches bit0 bit6 SRAM Asynchronous digital circuits 23
24 Dynamic Comparator pre-amplifier regenerative latch 2a eq 2a strobe Qn Qp strobe eq Vip Vin Qp Ready Vb Qn Dynamic to save power and generate ready signal Reset switches for fast recovery Ready signal is generated by NAND gate! 24
25 Metastable Issue '1' '1' large vid moderate vid vid~0 (metastable ) Cmp Outputs '1' '0' '0' '1' '0' '0' NAND gate threshold V FS Ready Signal If a comparison is stuck, SAR conversion won t be complete! 25
26 Sampling Network Series capacitor bank reduces input cap loading and settling time (C-2C network if α=β=2) 26
27 1.74 mm 250 µm Die Micrograph 1.4 mm 240 µm 27
28 Single Async. SAR ADC Resolution naturally tradeoffs with sampling rate! 28
29 Single Async. SAR w/ RF Input 29
30 Dual Async. SAR ADCs 30
31 Performance Summary Technology Package Resolution Sampling rate Supply voltage Input 3dB BW Peak SNDR INL/DNL 0.13-mm 6M CMOS Chip-on-board 6 bits MS/s for single ADC (600M-1GS/s for dual) 1.2 V > 4 GHz 34 db (f s = 600MS/s for dual ADC) 0.5 / -0.5 LSB Power Analog Digital Clock 1.2mW 3.2mW 0.9mW Total (dual ADC): 5.3mW 31
32 Comparison with SOA in 2006 High-speed (>10MS/s, 6-10b) ADCs from ISSCC (00-05 ) Total_PW F 2 ENOB s 32
33 Technology Scaling T track T comp T dig RC H ~1/S 1/f T ~1/S RC~1/S P analog P clk P dig IV~1/S fcv 2 ~[1/S-1/S 2 ] fcv 2 ~1/S 2 Constant field scaling (W,L,V dd 1/S) FOM (joule/conversion step) 1/S 2 33
34 Asynchronous SAR Advantages Asynchronous SAR architecture breaks the speed limit of conventional synchronous design methodology. Clock generation requirement is significantly relaxed. It was just the starting point many variations can be introduced potentially. 34
35 What s next? 1. Higher resolution approaching KT/C limit regime? 2. Higher speed GS/s sampling rate possible? 35
36 Higher Resolution Extension Traditional Asynchronous SAR V IN DAC Asynchronous SAR Logic Proposed Passive Gained Asynchronous SAR V IN DAC G Passive Asynchronous SAR Logic 36
37 Proposed Passive Gained SAR V N,Comp G Passive 1 Input referred Noise V IN DAC G Passive V N,Comp D OUT Asynchronous SAR Logic Key highlights 1. Passive amplifier(power-less) Comparator noise spec. 2. Redundant SAR operation Non-linear distortion due to parasitic Cap. 3. Passively amplified signal Comparison time 4. Embedding amplifier into DAC DAC settling time Full-scaled amplifying O 37
38 Proposed Passive Gain SAR V N,Comp G Passive Input referred Noise V IN DAC G Passive V N,Comp D OUT Key highlights Asynchronous SAR Logic 2 Converged to common mode at the final 1. Passive amplifier(power-less) Comparator noise spec. 2. Redundant SAR operation Non-linear distortion due to parasitic Cap. 3. Passively amplified signal Comparison time 4. Embedding amplifier into DAC DAC settling time Full-scaled amplifying O 38
39 Proposed Passive Gain SAR V N,Comp G Passive Input referred Noise V IN DAC G Passive V N,Comp D OUT Asynchronous SAR Logic Key highlights 3 xg Passive 1. Passive amplifier(power-less) Comparator noise spec. 2. Redundant SAR operation Non-linear distortion due to parasitic Cap. 3. Passively amplified signal Comparison time 4. Embedding amplifier into DAC DAC settling time Full-scaled amplifying O 39
40 Proposed Passive Gain SAR V N,Comp Input referred Noise 4 V IN G Passive DAC G Passive V N,Comp D OUT Asynchronous SAR Logic Key highlights 1. Passive amplifier(power-less) Comparator noise spec. 2. Redundant SAR operation Non-linear distortion due to parasitic Cap. 3. Passively amplified signal Comparison time 4. Embedding G Passive into DAC DAC settling time Rail-to-rail input swing 40
41 Embedded Passive Gain Operation Split Capacitor (Double Sampling) Stacked Capacitor (Amplification) V IN C S M S1 M S2 Gain Passive - + C S1 C S V IN + - C S1 C S2 C S 2 C S 2 41
42 Embedded Passive Gain Operation Split Capacitor (Double Sampling) Stacked Capacitor (Amplification) Subsequent SAR operation V IN C S M S1 M S2 Gain Passive - C S1 C S C S1-2V IN -2V IN +V tune + C S2 SAR Operation V tune C-DAC C S 2 Controlling only C S /2 during SAR operation DAC response speed C S 2 42
43 Voltage Over-range Issue Φ1 : Sampling V IN to C S1 & C S2 Φ2 : Charge Redistribution Φ1 Φ1 Φ2 V IN Φ1 Φ2 C S1 + V X Φ1 V IN Φ2 Φ1 C S2 + Φ1 V OUT +V FS /2 +V FS /2 +V FS /2 0 V IN 0 V X 0 V OUT - V FS /2 - V FS /2 - V FS /2 43
44 Voltage Over-range Issue Φ1 : Sampling V IN to C S1 & C S2 Φ2 : Charge Redistribution Φ1 Φ1 Φ2 V IN Φ1 Φ2 C S1 + V X Φ1 V IN Φ2 Φ1 C S2 + Not properly Turned off Φ1 V OUT Rail-to-rail Input Swing [X] +V FS /2 0 V IN +V FS /2 +V FS /2 0 V X 0 V OUT - V FS /2 - V FS /2 - V FS /2 44
45 Proposed Level Shifting V IN Φ1 Φ2 C S1 + V X Φ1 V IN Φ2 Φ1 Level Shifting Circuit C S2 + Comparator Φ1 V OUT Procedures (1) MSB decision by using C S2 (2) Performing Level shifting 45
46 Level Shift Up [MSB>0] CASE I : V IN = [ -V FS /2, 0 ] V FS /2 [MSB-1] Decision range Level shift up Φ1 Φ1 Φ2 Φ3 doubled V IN 0 V IN V FS /2 Φ1 x2 Performing at once V OUT C S2 + Comp. V IN Φ1 + C S1 Φ1 Φ3 C BAT Φ3 Φ2 Φ1 MSB (=D[1]) Φ3 46
47 Level Shift Down [MSB<0] CASE II : V IN = [ 0, V FS /2 ] V FS /2 [MSB-1] Decision range V IN Φ1 Φ1 Φ2 Φ3 doubled V IN 0 V FS /2 Φ1 x2 Level shift down Performing at once V OUT C S2 + Comp. V IN Φ1 + C S1 Φ1 Φ3 C BAT Φ3 Φ2 Φ1 MSB (=D[1]) Φ3 47
48 Free of Voltage Clipping + V FS /2 + V FS /2 + V FS /2 + V FS /2 V IN V X V Y V OUT - V FS /2 - V FS /2 - V FS /2 - V FS /2 V IN Φ1 C S2 + V OUT Comp. V IN Φ1 + C S1 Φ1 V X Φ3 C BAT Φ3 Φ2 Φ1 Φ3 V Y Allowing rail-to-rail input signal swing 48
49 Subsequent SAR Operation V DAC = 12 i=2 D OUT [i] Rx[i] i V REF C S1 C S2 V OUT V IN V IN V REF C BAT Φ2 Φ1 D[2:12] Φ1 D[1] 12 Asynchronous SAR Logic C S1 consists of non-binary weighted Cap arrays. 49
50 KT/C Noise Analysis V BAT C BAT Sampling Phase - + V IN - + Passive Gain Amplifying Phase V IN ±V BAT + - SNR i V IN KT C s Signal Amplitude: 2V IN RMS V[ KT/C Noise ] : 2 KT C s SNR O = SNR i C BAT C S 2 C S 2 C S 2 C BAT C S 2 Selecting large size of C BAT (SNR drops due to C BAT ) < 0.5dB Sufficiently large sized C BAT to prevent SNR degradation 50
51 Comparator VDD MP1 R1 R2 1st Stage MP2 MP3 MP4 MP5 MP6 2 nd Stage CK AMP CK RS Equalize Amplify S1 >> S2 CK AMP V O1N V O1P V O2P S2 V O2N S1 : S2 : ON ON OFF ON CK RS S1 CK RS CK AMP Latch V INP CK RS V INN CK RS V OUTP V OUTN MN1 MN2 MN3 MN4 MN5 MN6 I S1 I S2 CK AMP Dual sized switches Fast Reset (S1) Amplifying (S2) 51
52 Time-out Scheme Sampling Clock V INP V INN DAC V data_ready Earlier arrived pulse detected Normal Operation Loop SW_CTRL CK AMP, CK RS Time-out operation Loop CK RS Delay T time-out V time-out Asynchronous SAR logic Forcing the advancement of asynchronous conversion if comparator is stuck. 52
53 Time-out Timing Diagram SCLK Env_Conv T Conv 1 st 2 nd 3 rd 4 th N th CK Amp V data_ready T time-out Time-out detect V time-out V comp Comparator s threshold level Code V time-out forces next conversion (T time-out designed for worst case) 53
54 Chip Micrograph Bootstrap SW 280um C BAT CDAC P (C S1 ) Comparator CDAC N (C S1 ) C BAT 260um C S2 Async. SAR Logic C S2 Decimator Active Area: 280μm X 260μm J. Nam, D. Chiong, M. S.W. Chen, A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded Passive Gain in 65nm CMOS, CICC
55 [LSB] [LSB] Static Performance +1.0 DNL (+0.70/-0.84 LSB) [CODE] INL (+0.79/-0.84 LSB) [CODE]
56 ) Power (db) Power (db) Dynamic Performance After Radix Calibration* 0-40 f IN = 1.0 MHz, f S = 95 MHz ENOB = 10.2 SNDR = 63.1 db SFDR = 75.2 db -80 HD2 HD3 HD f S 32 2 f S 32 3 f S 32 4 f S 32 Normalized Frequency (ADC output decimated by 4x) SFDR 0 60 f S = 95 MHz SNDR M 20M 30M 40M 50M Input Frequency (Hz) 57.8 db f IN = 1.0 MHz, f S = 95 MHz SNDR = 63.1 db 56
57 Performance Summary ADC Topology f sampling Resolution Signal Bandwidth Supply (V) SFDR (db) SNDR (db) Power (mw) Asynchronous SAR with Passive Gain 95-MS/s 11-bit 47.5 MHz 1.1 V 75.2 db 63.1 db 1.36 mw Area (mm 2 ) mm 2 Process (nm) FoM 65 nm CMOS 22 Nyquist 14 Low Freq. 57
58 FoM [fj/step] Comparison to prior art ISSCC VLSI Filtering with > 10.0 ENOB, > 10MS/s This work 10.2 ENOB Nyquist) Low Freq.) M 40M 60M 80M 100M f sample Achieves the lowest FoM among recently published ADCs ( >10ENOB, > 10MS/s ) 58
59 Higher Speed Extension What if higher speed is demanded? 1. Unrolled comparators 2. Asynchronous DAC settling 3. Multi-bit/cycle 4. Pipelining 5. Time interleaving 59
60 Unrolled Comparators Unroll the comparators No comparator reset No DAC settling 60
61 Unrolled Asynchronous SAR G. Van der Plas, et al, A 150 MS/s 133 uw 7 bit ADC in 90 nm Digital CMOS, JSSC,
62 Asynchronous DAC Settling DAC settling can also be asynchronous R. Kapusta, et al., A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS, ISSCC
63 - Fewer cycles required for conversion Multi-bit/cycle Conversion - Time-to-digital converter can assist bit comparison But -Give away the offset tolerance -Opportunities for calibration 63
64 Pipelining Residue voltage is available on capacitor network for free 64
65 Time Interleaving Sampling rate scale proportionally to the number of interleaved channels Calibration is required for inter-channel mismatch Relaxed clock distribution For example: 8bit 56GS/s 320 of 175MS/s SAR (Fujitsu) 65
66 90GS/s 8bit with 64x Time Interleave Two comparators ping pong in two consecutive conversions implemented in 32nm SOI L. Kull, et al., A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS, ISSCC
67 Family of Asynchronous SAR High-speed (>10MS/s, 5-10b) ADCs from ISSCC (00-10 ) Asynchronous SAR has been widely adopted since Benefit from technology scaling! Total_PW F 2 ENOB s Latest: 8b, 90GS/s, 200 fj/conv-step ISSCC 2014 Family of Async. Enabled ADC 67
68 Future Asynchronous SAR The trend is going towards 1-100GS/s ADC. Power efficiency is going towards the order of 1-10 fj/conv-step. Total_PW F 2 ENOB s Latest: 8b, 90GS/s, 200 fj/conv-step ISSCC 2014 Future Breakthroughs! 68
69 Conclusion Low-power, high-speed ADCs are in great needs. New opportunities and breakthroughs are expected in accelerated rate. Asynchronous SAR ADC architecture provides power efficient platform for achieving this goal. The record high-speed (90GS/s) ADC also leverages this topology. More variations of asynchronous SAR ADC architecture will come from all of you! 69
70 Acknowledgements All PhD students involved in these projects: Jaewon Nam, Praveen Sharma and David Chiong. ONR for funding supports. 70
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