AD9772A - Functional Block Diagram

Transcription

1 F FEATURES single 3.0 V to 3.6 V supply 14-Bit DAC Resolution 160 MPS Input Data Rate 67.5 MHz Reconstruction 160 MPS 74 dbc 25 MHz 2 Interpolation Filter with High- or Low-Pass Response 73 db Image Rejection with db Passband Ripple Zero- tuffing Option for Enhanced Direct IF Performance Internal 2/4 Clock Multiplier 250 mw Power Dissipation; 13 mw with Power-Down Mode APPLICATIONS Communication Transmit Channel W-CDMA Base stations, Multicarrier Base stations, Direct IF synthesis, Wideband Cable Systems Instrumentation AD9772A - Functional Block Diagram 1

2 AD PRODUCT HIGHLIGHTS A flexible, low power 2 interpolation filter supporting reconstruction bandwidths of up to 67.5 MHz can be configured for a low- or highpass response with 73 db of image rejection for traditional baseband or direct IF applications. A zero-stuffing option enhances direct IF applications. A low glitch, fast settling 14-bit DAC provides exceptional dynamic range for both baseband and direct IF waveform reconstruction applications. The AD9772A digital interface, consisting of edge-triggered latches and a flexible differential or single-ended clock input, can support input data rates up to 160 MSPS. On-chip PLL clock multiplier generates all of the internal high-speed clocks required by the interpolation filter and DAC. The current output(s) of the AD9772A can easily be configured for various single-ended or differential circuit topologies. TxDAC+ is a registered trademark of Analog Devices, Inc. AD9772A DC SPECIFICATIONS Parameter Min Typ Max Unit RESOLUTION 14 Bits DC ACCURACY Integral Linearity Error (INL) ±3.5 LSB Differential Nonlinearity (DNL) ±2.0 LSB Monotonicity (12-Bit) Guaranteed Over Specified Temp. Range ANALOG OUTPUT Offset Error % of FSR Gain Error (No Int. Ref.) 2 ± % of FSR Gain Error (With Int. Ref.) 5 ± % of FSR Full-Scale Output Current 2 20 ma Output Compliance Range V Output Resistance 200 kohm Output Capacitance 3 pf REFERENCE OUTPUT Reference Voltage V Reference Output Current 1 µa 2

3 AD9772A Dynamic SPECIFICATIONS Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fdac) 400 MSPS Output Settling Time (tst) (to 0.025%) 11 ns Output Propagation Delay 1 (tpd) 17 ns Output Rise Time (10% to 90%) 0.8 ns Output Fall Time (10% to 90%) 0.8 ns Output Noise (IOUTFS = 20 ma) 50 pa Hz -1/2 AC LINEARITY BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fout = 0 dbfs) fdata = 65 MSPS; fout = 1.01 MHz 82 dbc fdata = 65 MSPS; fout = MHz 75 dbc fdata = 65 MSPS; fout = MHz 73 dbc fdata = 160 MSPS; fout = 5.02 MHz 82 dbc fdata = 160 MSPS; fout = MHz 75 dbc (The difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth) Digital modes 3

4 AD9772A Time and Frequency Domain Example of Low-Pass 2 Digital Interpolation Filter AD9772A Time and Frequency Domain Example of High-Pass 2 Digital Interpolation Filter 4

5 AD9772A Zero stuffing for Direct IF conversion Block Diagram of Internal DAC, 1.2 V Reference, and Reference Control Circuits 5

6 Equivalent output circuit FEATURES 250 MSPS Update Rate Low Glitch Impulse Complete Composite Functions Internal Voltage Reference Single 5.2 V Supply APPLICATIONS Raster Scan Displays Color Graphics Automated Test Equipment TV Video Reconstruction GENERAL DESCRIPTION The AD9701 is a high speed, 8- bit digital-to-analog converter with fully integrated composite video functions. High speed ECL input registers provide synchronous operation of data and control functions up to 250 MSPS. 6

7 AD9701 Functional Block Diagram ELECTRICAL CHARACTERISTICS AD9701BQ RESOLUTION 8 Bits DC ACCURACY Differential Linearity (+25 C) 0.25 LSB Integral Linearity (+25 C) 0.25 LSB Monotonicity Guaranteed INITIAL OFFSET ERROR Zero-Scale Offset Error (+25 C) 0.05 mv Zero-Scale Offset Drift Coefficient 2 µv/ C DYNAMIC PERFORMANCE Update Rate (+25 C) 225 MSPS Output Propagation Delay (+25 C) 5 ns Output Settling Time Current (+25 C) 8 ns Voltage (+25 C) 12 ns Output Slew Rate (+25 C) 255 V/µs Glitch Impulse (+25 C) 60 pv-s 7

8 ELECTRICAL CHARACTERISTICS AD9701BQ DIGITAL INPUTS Logic 1 Voltage 1.1 V Logic 0 Voltage 1.5 V Logic 1 Current 100 ma Logic 0 Current 15 ma Input Capacitance (+25 C) 4 pf Data Setup Time (+25 C) 0.1 ns Data Hold Time `(+25 C) 1.4 ns Supply Voltages = 5.2 V; RL = 37.5 Ohm; FEATURE 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal 2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three- State CMOS Outputs Single or Demultiplexed Output Ports Data Clock Output Provided Low Power: 1.0 W Typical 5 V Converter Power Supply APPLICATION RGB Graphics Processing High Resolution Video LCD Monitors and Projectors Micromirror Projectors Plasma Display Panels 8

9 The AD9483 is a triple 8-bit monolithic analog-to-digital converter optimized for digitizing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports display resolutions of up to at 75 Hz with sufficient input bandwidth to accurately acquire and digitize each pixel. The digital outputs are three-state CMOS outputs. Separate output power supply pins support interfacing with 3.3 V or 5 V logic. Fabricated in an advanced BiCMOS process, the AD9483 is provided in a space-saving 100-lead MQFP surface mount plastic package (S-100) and is specified over the 0 C to 85 C temperature range. AD Functional Block Diagram 9

10 AD9483 KS140 DC Specifications Parameter Min Typ Max Unit RESOLUTION 8 Bits DC ACCURACY Differential Nonlinearity 25 C / 1.0 LSB Integral Nonlinearity 25 C / 1.50 LSB No Missing Codes Guaranteed Gain Error 25 C ±1 ±2 % FS ANALOG INPUT Input Voltage Range ±512 mv p p Input Offset Voltage 25 C ±4 ±16 mv Input Resistance (25 C) kohm Input Bias Current 25 C µa Analog Bandwidth, Full Power 25 C MHz AD9483 KS140 Dynamic Specifications Parameter Min Typ Max Unit Maximum Conversion Rate 140 MSPS Minimum Conversion Rate 100 MSPS Signal-to-Noise Ratio (SNR) (Without Harmonics) fin = 19.7 MHz 25 C 45 db fin = 49.7 MHz 25 C db fin = 69.7 MHz 25 C 44 db Signal-to-Noise Ratio (SINAD) (With Harmonics) fin = 19.7 MHz 25 C 44 db fin = 49.7 MHz 25 C db fin = 69.7 MHz 25 C 42 db Effective Number of Bits fin = 19.7 MHz 25 C 7.0 Bits fin = 49.7 MHz 25 C Bits fin = 69.7 MHz 25 C 6.8 Bits 10

11 AD9843 Timing Single Channel Mode Pipelined Flash (2 x 4bit Flash ADCs) latency 4 clock periods - AD9843 SNR and SINAD 11

12 Theory of Operation The AD9483 combines Analog Devices patented MagAmp bit-per-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on board reference and input logic that accepts TTL, CMOS or PECL levels. Each of the three analog input signals is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and com-bined into the 8-bit result. FEATURES 22-Bit Sigma-Delta ADC Dynamic Range of 105 db (146 Hz Input) % Integral Nonlinearity On-Chip Low-Pass Digital Filter Cutoff Programmable from 584 Hz to 36.5 Hz Linear Phase Response Five Line Serial I/O Twos Complement Coding Easy Interface to DSPs and Microcomputers Software Control of Filter Cutoff +- 5 V Supply Low Power Operation: 50 mw APPLICATIONS Biomedical Data Acquisition ECG Machines EEG Machines Process Control High Accuracy Instrumentation Seismic Systems 12

13 General Description The AD7716 is a signal processing block for data acquisition systems. It is capable of processing four channels with band-widths of up to 584 Hz. Resolution is 22 bits and the usable dynamic range varies from 111 db with an input bandwidth of 36.5 Hz to 99 db with an input bandwidth of 584 Hz. The device consists of four separate A/D converter channels that are implemented using sigma-delta technology. Sigma-delta ADCs include on-chip digital filtering and, thus, the system filtering requirements are eased. Three address pins program the device address. This allows a data acquisition system with up to 32 channels to be set up in a simple fashion. The output word from the device contains 32 bits of data. One bit is determined by the state of the DIN1 in-put and may be used, for example, in an ECG system with an external pacemaker detect circuit to indicate that the output word is invalid because of the presence of a pacemaker pulse. Functional Block Diagram 13

14 AD7716 SPECIFICATIONS fclkin = 8 MHz; AVDD = DVDD = +5 V, AVSS = 5 V ; AGND = DGND = 0 V; VREF = 2.5 V; Filter Cutoff = 146 Hz; Noise Measurement Bandwidth = 146 Hz STATIC PERFORMANCE B Version Units Resolution 22 Bits Integral Linearity Error % FSR Guaranteed No Missed Codes Gain Error 1 %FSR max Gain Match Between Channels 0.5 % FSR max Offset Error 0.2 % FSR max Offset Match Between Channels 0.1 % FSR max Noise 11 mv rms max AD7716 DYNAMIC SPECIFICATIONS Sampling Rate fclkin/ khz for fclkin = 8 MHz Output Update Rate fclkin/(14 x 256 x 2 N ) Filter Cutoff Frequency fclkin/(3.81x14x256x2 N ) Settling Time (3x14x256x2 N /fclkin) Total Harmonic Distortion 90 db typ Input Frequency = 35 Hz Channel-to-Channel Isolation 85 db typ Feedthrough from Any One Channel to the Other Three, with 35 Hz Full-Scale Sine Wave Applied to that Channel ANALOG INPUT Input Range ±2.5 Volts Input Capacitance 10 pf typ Input Bias Current 1 na typ 14

15 AD7716 Operation The AD7716 uses a second-order sigma-delta modulator and a digital filter that provides a rolling average of the sampled out-put. After power-up or if there is a step change in the input voltage, there is a settling time before valid data is obtained. Filter Characteristics The cutoff frequency of the digital filter is determined by bits FC2, FC1 and FC0 in the control register (See Table IV). The cutoff frequency of the filter is fclkin /(3.81x14x256x2 N ), where N is the decimal equivalent of FC2, FC1, FC0. At the maximum clock frequency of 8 MHz, with all 0s loaded to FC2, FC1, FC0, the cutoff frequency of the filter is 584 Hz and the data update rate is 2232 Hz. Since the AD7716 contains low-pass filtering, there is a settling time associated with step function inputs, and data will be in-valid after a step change until the settling time has elapsed. AD7716 Operation Post Filtering In the AD7716, the onchip modulator provides the digital filter with samples at a rate of 570 khz. The filter decimates these samples to provide data at an output rate which corresponds to the programmed first notch frequency of the filter. 15